drm/i915/dg2: Update lane disable power state during PSR

The PSR enable/disable sequences now require that we program an extra
register in the PHY to adjust the lane disable power setting.

Bspec: 49274
Bspec: 53885
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-29-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 9393b35cd44490cde7b78600e35a046077989df9..1b0daf649e82393116a1ede14282abd1d025a31a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -32,6 +32,7 @@
 #include "intel_dp_aux.h"
 #include "intel_hdmi.h"
 #include "intel_psr.h"
+#include "intel_snps_phy.h"
 #include "intel_sprite.h"
 #include "skl_universal_plane.h"
 
@@ -1212,6 +1213,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 {
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+       enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
        struct intel_encoder *encoder = &dig_port->base;
        u32 val;
 
@@ -1237,6 +1239,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
        intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
                                     &intel_dp->psr.vsc);
        intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc);
+       intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
        intel_psr_enable_sink(intel_dp);
        intel_psr_enable_source(intel_dp);
        intel_dp->psr.enabled = true;
@@ -1333,6 +1336,8 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
 static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 {
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+       enum phy phy = intel_port_to_phy(dev_priv,
+                                        dp_to_dig_port(intel_dp)->base.port);
 
        lockdep_assert_held(&intel_dp->psr.lock);
 
@@ -1358,6 +1363,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
                             TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
                             TRANS_SET_CONTEXT_LATENCY_MASK, 0);
 
+       intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
+
        /* Disable PSR on Sink */
        drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
 

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index f0c30d3d2dfbba2fbf9bce04ba6cc8e7222331a1..18b52b64af955aa8c003bb48f07450b13021fff7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -36,6 +36,20 @@ void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv)
        }
 }
 
+void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv,
+                                          enum phy phy, bool enable)
+{
+       u32 val;
+
+       if (!intel_phy_is_snps(dev_priv, phy))
+               return;
+
+       val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR,
+                            enable ? 2 : 3);
+       intel_uncore_rmw(&dev_priv->uncore, SNPS_PHY_TX_REQ(phy),
+                        SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val);
+}
+
 static const u32 dg2_ddi_translations[] = {
        /* VS 0, pre-emph 0 */
        REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 26),

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h
index 6aa33ff729ec9580211e5b865b6d6ca08dfd46a4..6261ff88ef5c6ed056916874a4b7975d6d8f76e6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h
@@ -12,8 +12,11 @@ struct drm_i915_private;
 struct intel_encoder;
 struct intel_crtc_state;
 struct intel_mpllb_state;
+enum phy;
 
 void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv);
+void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv,
+                                          enum phy phy, bool enable);
 
 int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
                           struct intel_encoder *encoder);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7306832921f89d4d4289e46dae08c48f06edb807..51301fa9da1476d2590d45d591576a23a89420ed 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2332,6 +2332,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define SNPS_PHY_REF_CONTROL(phy)              _MMIO_SNPS(phy, 0x168188)
 #define   SNPS_PHY_REF_CONTROL_REF_RANGE       REG_GENMASK(31, 27)
 
+#define SNPS_PHY_TX_REQ(phy)                   _MMIO_SNPS(phy, 0x168200)
+#define   SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
+
 #define SNPS_PHY_TX_EQ(ln, phy)                        _MMIO_SNPS_LN(ln, phy, 0x168300)
 #define   SNPS_PHY_TX_EQ_MAIN                  REG_GENMASK(23, 18)
 #define   SNPS_PHY_TX_EQ_POST                  REG_GENMASK(15, 10)