x86/hyper-v: move hyperv.h out of uapi
authorVitaly Kuznetsov <vkuznets@redhat.com>
Tue, 20 Mar 2018 14:02:05 +0000 (15:02 +0100)
committerRadim Krčmář <rkrcmar@redhat.com>
Wed, 28 Mar 2018 20:47:06 +0000 (22:47 +0200)
hyperv.h is not part of uapi, there are no (known) users outside of kernel.
We are making changes to this file to match current Hyper-V Hypervisor
Top-Level Functional Specification (TLFS, see:
https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs)
and we don't want to maintain backwards compatibility.

Move the file renaming to hyperv-tlfs.h to avoid confusing it with
mshyperv.h. In future, all definitions from TLFS should go to it and
all kernel objects should go to mshyperv.h or include/linux/hyperv.h.

Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
13 files changed:
MAINTAINERS
arch/x86/hyperv/hv_init.c
arch/x86/include/asm/hyperv-tlfs.h [new file with mode: 0644]
arch/x86/include/asm/kvm_host.h
arch/x86/include/asm/mshyperv.h
arch/x86/include/uapi/asm/hyperv.h [deleted file]
arch/x86/include/uapi/asm/kvm_para.h
arch/x86/kernel/cpu/mshyperv.c
drivers/hv/connection.c
drivers/hv/hv.c
drivers/hv/hyperv_vmbus.h
drivers/hv/vmbus_drv.c
include/linux/hyperv.h

index 4623caf8d72d8591b87a300b35b5ad0aca10f6a5..80befd9f4775e2adb7c44468a987fadc42819b9f 100644 (file)
@@ -6531,7 +6531,7 @@ S:        Maintained
 F:     Documentation/networking/netvsc.txt
 F:     arch/x86/include/asm/mshyperv.h
 F:     arch/x86/include/asm/trace/hyperv.h
-F:     arch/x86/include/uapi/asm/hyperv.h
+F:     arch/x86/include/asm/hyperv-tlfs.h
 F:     arch/x86/kernel/cpu/mshyperv.c
 F:     arch/x86/hyperv
 F:     drivers/hid/hid-hyperv.c
index 2edc49e7409baa9b3bfa6b9991247656001a0277..4b82bc20692961708d1b65e227d63e5bf3e2bbaf 100644 (file)
@@ -21,7 +21,7 @@
 #include <asm/apic.h>
 #include <asm/desc.h>
 #include <asm/hypervisor.h>
-#include <asm/hyperv.h>
+#include <asm/hyperv-tlfs.h>
 #include <asm/mshyperv.h>
 #include <linux/version.h>
 #include <linux/vmalloc.h>
diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h
new file mode 100644 (file)
index 0000000..77d6e8b
--- /dev/null
@@ -0,0 +1,432 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+
+/*
+ * This file contains definitions from Hyper-V Hypervisor Top-Level Functional
+ * Specification (TLFS):
+ * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
+ */
+
+#ifndef _ASM_X86_HYPERV_TLFS_H
+#define _ASM_X86_HYPERV_TLFS_H
+
+#include <linux/types.h>
+
+/*
+ * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
+ * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
+ */
+#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS  0x40000000
+#define HYPERV_CPUID_INTERFACE                 0x40000001
+#define HYPERV_CPUID_VERSION                   0x40000002
+#define HYPERV_CPUID_FEATURES                  0x40000003
+#define HYPERV_CPUID_ENLIGHTMENT_INFO          0x40000004
+#define HYPERV_CPUID_IMPLEMENT_LIMITS          0x40000005
+
+#define HYPERV_HYPERVISOR_PRESENT_BIT          0x80000000
+#define HYPERV_CPUID_MIN                       0x40000005
+#define HYPERV_CPUID_MAX                       0x4000ffff
+
+/*
+ * Feature identification. EAX indicates which features are available
+ * to the partition based upon the current partition privileges.
+ */
+
+/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
+#define HV_X64_MSR_VP_RUNTIME_AVAILABLE                (1 << 0)
+/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
+#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE    (1 << 1)
+/* Partition reference TSC MSR is available */
+#define HV_X64_MSR_REFERENCE_TSC_AVAILABLE              (1 << 9)
+
+/* A partition's reference time stamp counter (TSC) page */
+#define HV_X64_MSR_REFERENCE_TSC               0x40000021
+
+/*
+ * There is a single feature flag that signifies if the partition has access
+ * to MSRs with local APIC and TSC frequencies.
+ */
+#define HV_X64_ACCESS_FREQUENCY_MSRS           (1 << 11)
+
+/* AccessReenlightenmentControls privilege */
+#define HV_X64_ACCESS_REENLIGHTENMENT          BIT(13)
+
+/*
+ * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
+ * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
+ */
+#define HV_X64_MSR_SYNIC_AVAILABLE             (1 << 2)
+/*
+ * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
+ * HV_X64_MSR_STIMER3_COUNT) available
+ */
+#define HV_X64_MSR_SYNTIMER_AVAILABLE          (1 << 3)
+/*
+ * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
+ * are available
+ */
+#define HV_X64_MSR_APIC_ACCESS_AVAILABLE       (1 << 4)
+/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
+#define HV_X64_MSR_HYPERCALL_AVAILABLE         (1 << 5)
+/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
+#define HV_X64_MSR_VP_INDEX_AVAILABLE          (1 << 6)
+/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
+#define HV_X64_MSR_RESET_AVAILABLE             (1 << 7)
+ /*
+  * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
+  * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
+  * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
+  */
+#define HV_X64_MSR_STAT_PAGES_AVAILABLE                (1 << 8)
+
+/* Frequency MSRs available */
+#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE    (1 << 8)
+
+/* Crash MSR available */
+#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
+
+/*
+ * Feature identification: EBX indicates which flags were specified at
+ * partition creation. The format is the same as the partition creation
+ * flag structure defined in section Partition Creation Flags.
+ */
+#define HV_X64_CREATE_PARTITIONS               (1 << 0)
+#define HV_X64_ACCESS_PARTITION_ID             (1 << 1)
+#define HV_X64_ACCESS_MEMORY_POOL              (1 << 2)
+#define HV_X64_ADJUST_MESSAGE_BUFFERS          (1 << 3)
+#define HV_X64_POST_MESSAGES                   (1 << 4)
+#define HV_X64_SIGNAL_EVENTS                   (1 << 5)
+#define HV_X64_CREATE_PORT                     (1 << 6)
+#define HV_X64_CONNECT_PORT                    (1 << 7)
+#define HV_X64_ACCESS_STATS                    (1 << 8)
+#define HV_X64_DEBUGGING                       (1 << 11)
+#define HV_X64_CPU_POWER_MANAGEMENT            (1 << 12)
+#define HV_X64_CONFIGURE_PROFILER              (1 << 13)
+
+/*
+ * Feature identification. EDX indicates which miscellaneous features
+ * are available to the partition.
+ */
+/* The MWAIT instruction is available (per section MONITOR / MWAIT) */
+#define HV_X64_MWAIT_AVAILABLE                         (1 << 0)
+/* Guest debugging support is available */
+#define HV_X64_GUEST_DEBUGGING_AVAILABLE               (1 << 1)
+/* Performance Monitor support is available*/
+#define HV_X64_PERF_MONITOR_AVAILABLE                  (1 << 2)
+/* Support for physical CPU dynamic partitioning events is available*/
+#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE      (1 << 3)
+/*
+ * Support for passing hypercall input parameter block via XMM
+ * registers is available
+ */
+#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE          (1 << 4)
+/* Support for a virtual guest idle state is available */
+#define HV_X64_GUEST_IDLE_STATE_AVAILABLE              (1 << 5)
+/* Guest crash data handler available */
+#define HV_X64_GUEST_CRASH_MSR_AVAILABLE               (1 << 10)
+
+/*
+ * Implementation recommendations. Indicates which behaviors the hypervisor
+ * recommends the OS implement for optimal performance.
+ */
+ /*
+  * Recommend using hypercall for address space switches rather
+  * than MOV to CR3 instruction
+  */
+#define HV_X64_AS_SWITCH_RECOMMENDED           (1 << 0)
+/* Recommend using hypercall for local TLB flushes rather
+ * than INVLPG or MOV to CR3 instructions */
+#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED     (1 << 1)
+/*
+ * Recommend using hypercall for remote TLB flushes rather
+ * than inter-processor interrupts
+ */
+#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED    (1 << 2)
+/*
+ * Recommend using MSRs for accessing APIC registers
+ * EOI, ICR and TPR rather than their memory-mapped counterparts
+ */
+#define HV_X64_APIC_ACCESS_RECOMMENDED         (1 << 3)
+/* Recommend using the hypervisor-provided MSR to initiate a system RESET */
+#define HV_X64_SYSTEM_RESET_RECOMMENDED                (1 << 4)
+/*
+ * Recommend using relaxed timing for this partition. If used,
+ * the VM should disable any watchdog timeouts that rely on the
+ * timely delivery of external interrupts
+ */
+#define HV_X64_RELAXED_TIMING_RECOMMENDED      (1 << 5)
+
+/*
+ * Virtual APIC support
+ */
+#define HV_X64_DEPRECATING_AEOI_RECOMMENDED    (1 << 9)
+
+/* Recommend using the newer ExProcessorMasks interface */
+#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED  (1 << 11)
+
+/*
+ * Crash notification flag.
+ */
+#define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63)
+
+/* MSR used to identify the guest OS. */
+#define HV_X64_MSR_GUEST_OS_ID                 0x40000000
+
+/* MSR used to setup pages used to communicate with the hypervisor. */
+#define HV_X64_MSR_HYPERCALL                   0x40000001
+
+/* MSR used to provide vcpu index */
+#define HV_X64_MSR_VP_INDEX                    0x40000002
+
+/* MSR used to reset the guest OS. */
+#define HV_X64_MSR_RESET                       0x40000003
+
+/* MSR used to provide vcpu runtime in 100ns units */
+#define HV_X64_MSR_VP_RUNTIME                  0x40000010
+
+/* MSR used to read the per-partition time reference counter */
+#define HV_X64_MSR_TIME_REF_COUNT              0x40000020
+
+/* MSR used to retrieve the TSC frequency */
+#define HV_X64_MSR_TSC_FREQUENCY               0x40000022
+
+/* MSR used to retrieve the local APIC timer frequency */
+#define HV_X64_MSR_APIC_FREQUENCY              0x40000023
+
+/* Define the virtual APIC registers */
+#define HV_X64_MSR_EOI                         0x40000070
+#define HV_X64_MSR_ICR                         0x40000071
+#define HV_X64_MSR_TPR                         0x40000072
+#define HV_X64_MSR_APIC_ASSIST_PAGE            0x40000073
+
+/* Define synthetic interrupt controller model specific registers. */
+#define HV_X64_MSR_SCONTROL                    0x40000080
+#define HV_X64_MSR_SVERSION                    0x40000081
+#define HV_X64_MSR_SIEFP                       0x40000082
+#define HV_X64_MSR_SIMP                                0x40000083
+#define HV_X64_MSR_EOM                         0x40000084
+#define HV_X64_MSR_SINT0                       0x40000090
+#define HV_X64_MSR_SINT1                       0x40000091
+#define HV_X64_MSR_SINT2                       0x40000092
+#define HV_X64_MSR_SINT3                       0x40000093
+#define HV_X64_MSR_SINT4                       0x40000094
+#define HV_X64_MSR_SINT5                       0x40000095
+#define HV_X64_MSR_SINT6                       0x40000096
+#define HV_X64_MSR_SINT7                       0x40000097
+#define HV_X64_MSR_SINT8                       0x40000098
+#define HV_X64_MSR_SINT9                       0x40000099
+#define HV_X64_MSR_SINT10                      0x4000009A
+#define HV_X64_MSR_SINT11                      0x4000009B
+#define HV_X64_MSR_SINT12                      0x4000009C
+#define HV_X64_MSR_SINT13                      0x4000009D
+#define HV_X64_MSR_SINT14                      0x4000009E
+#define HV_X64_MSR_SINT15                      0x4000009F
+
+/*
+ * Synthetic Timer MSRs. Four timers per vcpu.
+ */
+#define HV_X64_MSR_STIMER0_CONFIG              0x400000B0
+#define HV_X64_MSR_STIMER0_COUNT               0x400000B1
+#define HV_X64_MSR_STIMER1_CONFIG              0x400000B2
+#define HV_X64_MSR_STIMER1_COUNT               0x400000B3
+#define HV_X64_MSR_STIMER2_CONFIG              0x400000B4
+#define HV_X64_MSR_STIMER2_COUNT               0x400000B5
+#define HV_X64_MSR_STIMER3_CONFIG              0x400000B6
+#define HV_X64_MSR_STIMER3_COUNT               0x400000B7
+
+/* Hyper-V guest crash notification MSR's */
+#define HV_X64_MSR_CRASH_P0                    0x40000100
+#define HV_X64_MSR_CRASH_P1                    0x40000101
+#define HV_X64_MSR_CRASH_P2                    0x40000102
+#define HV_X64_MSR_CRASH_P3                    0x40000103
+#define HV_X64_MSR_CRASH_P4                    0x40000104
+#define HV_X64_MSR_CRASH_CTL                   0x40000105
+#define HV_X64_MSR_CRASH_CTL_NOTIFY            (1ULL << 63)
+#define HV_X64_MSR_CRASH_PARAMS                \
+               (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
+
+/* TSC emulation after migration */
+#define HV_X64_MSR_REENLIGHTENMENT_CONTROL     0x40000106
+
+struct hv_reenlightenment_control {
+       __u64 vector:8;
+       __u64 reserved1:8;
+       __u64 enabled:1;
+       __u64 reserved2:15;
+       __u64 target_vp:32;
+};
+
+#define HV_X64_MSR_TSC_EMULATION_CONTROL       0x40000107
+#define HV_X64_MSR_TSC_EMULATION_STATUS                0x40000108
+
+struct hv_tsc_emulation_control {
+       __u64 enabled:1;
+       __u64 reserved:63;
+};
+
+struct hv_tsc_emulation_status {
+       __u64 inprogress:1;
+       __u64 reserved:63;
+};
+
+#define HV_X64_MSR_HYPERCALL_ENABLE            0x00000001
+#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT        12
+#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \
+               (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
+
+/* Declare the various hypercall operations. */
+#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE     0x0002
+#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST      0x0003
+#define HVCALL_NOTIFY_LONG_SPIN_WAIT           0x0008
+#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX  0x0013
+#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX   0x0014
+#define HVCALL_POST_MESSAGE                    0x005c
+#define HVCALL_SIGNAL_EVENT                    0x005d
+
+#define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE             0x00000001
+#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT      12
+#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK       \
+               (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
+
+#define HV_X64_MSR_TSC_REFERENCE_ENABLE                0x00000001
+#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12
+
+#define HV_PROCESSOR_POWER_STATE_C0            0
+#define HV_PROCESSOR_POWER_STATE_C1            1
+#define HV_PROCESSOR_POWER_STATE_C2            2
+#define HV_PROCESSOR_POWER_STATE_C3            3
+
+#define HV_FLUSH_ALL_PROCESSORS                        BIT(0)
+#define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES    BIT(1)
+#define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY      BIT(2)
+#define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT     BIT(3)
+
+enum HV_GENERIC_SET_FORMAT {
+       HV_GENERIC_SET_SPARCE_4K,
+       HV_GENERIC_SET_ALL,
+};
+
+/* hypercall status code */
+#define HV_STATUS_SUCCESS                      0
+#define HV_STATUS_INVALID_HYPERCALL_CODE       2
+#define HV_STATUS_INVALID_HYPERCALL_INPUT      3
+#define HV_STATUS_INVALID_ALIGNMENT            4
+#define HV_STATUS_INVALID_PARAMETER            5
+#define HV_STATUS_INSUFFICIENT_MEMORY          11
+#define HV_STATUS_INVALID_PORT_ID              17
+#define HV_STATUS_INVALID_CONNECTION_ID                18
+#define HV_STATUS_INSUFFICIENT_BUFFERS         19
+
+typedef struct _HV_REFERENCE_TSC_PAGE {
+       __u32 tsc_sequence;
+       __u32 res1;
+       __u64 tsc_scale;
+       __s64 tsc_offset;
+} HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
+
+/* Define the number of synthetic interrupt sources. */
+#define HV_SYNIC_SINT_COUNT            (16)
+/* Define the expected SynIC version. */
+#define HV_SYNIC_VERSION_1             (0x1)
+/* Valid SynIC vectors are 16-255. */
+#define HV_SYNIC_FIRST_VALID_VECTOR    (16)
+
+#define HV_SYNIC_CONTROL_ENABLE                (1ULL << 0)
+#define HV_SYNIC_SIMP_ENABLE           (1ULL << 0)
+#define HV_SYNIC_SIEFP_ENABLE          (1ULL << 0)
+#define HV_SYNIC_SINT_MASKED           (1ULL << 16)
+#define HV_SYNIC_SINT_AUTO_EOI         (1ULL << 17)
+#define HV_SYNIC_SINT_VECTOR_MASK      (0xFF)
+
+#define HV_SYNIC_STIMER_COUNT          (4)
+
+/* Define synthetic interrupt controller message constants. */
+#define HV_MESSAGE_SIZE                        (256)
+#define HV_MESSAGE_PAYLOAD_BYTE_COUNT  (240)
+#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30)
+
+/* Define hypervisor message types. */
+enum hv_message_type {
+       HVMSG_NONE                      = 0x00000000,
+
+       /* Memory access messages. */
+       HVMSG_UNMAPPED_GPA              = 0x80000000,
+       HVMSG_GPA_INTERCEPT             = 0x80000001,
+
+       /* Timer notification messages. */
+       HVMSG_TIMER_EXPIRED                     = 0x80000010,
+
+       /* Error messages. */
+       HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
+       HVMSG_UNRECOVERABLE_EXCEPTION   = 0x80000021,
+       HVMSG_UNSUPPORTED_FEATURE               = 0x80000022,
+
+       /* Trace buffer complete messages. */
+       HVMSG_EVENTLOG_BUFFERCOMPLETE   = 0x80000040,
+
+       /* Platform-specific processor intercept messages. */
+       HVMSG_X64_IOPORT_INTERCEPT              = 0x80010000,
+       HVMSG_X64_MSR_INTERCEPT         = 0x80010001,
+       HVMSG_X64_CPUID_INTERCEPT               = 0x80010002,
+       HVMSG_X64_EXCEPTION_INTERCEPT   = 0x80010003,
+       HVMSG_X64_APIC_EOI                      = 0x80010004,
+       HVMSG_X64_LEGACY_FP_ERROR               = 0x80010005
+};
+
+/* Define synthetic interrupt controller message flags. */
+union hv_message_flags {
+       __u8 asu8;
+       struct {
+               __u8 msg_pending:1;
+               __u8 reserved:7;
+       };
+};
+
+/* Define port identifier type. */
+union hv_port_id {
+       __u32 asu32;
+       struct {
+               __u32 id:24;
+               __u32 reserved:8;
+       } u;
+};
+
+/* Define synthetic interrupt controller message header. */
+struct hv_message_header {
+       __u32 message_type;
+       __u8 payload_size;
+       union hv_message_flags message_flags;
+       __u8 reserved[2];
+       union {
+               __u64 sender;
+               union hv_port_id port;
+       };
+};
+
+/* Define synthetic interrupt controller message format. */
+struct hv_message {
+       struct hv_message_header header;
+       union {
+               __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
+       } u;
+};
+
+/* Define the synthetic interrupt message page layout. */
+struct hv_message_page {
+       struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
+};
+
+/* Define timer message payload structure. */
+struct hv_timer_message_payload {
+       __u32 timer_index;
+       __u32 reserved;
+       __u64 expiration_time;  /* When the timer expired */
+       __u64 delivery_time;    /* When the message was delivered */
+};
+
+#define HV_STIMER_ENABLE               (1ULL << 0)
+#define HV_STIMER_PERIODIC             (1ULL << 1)
+#define HV_STIMER_LAZY                 (1ULL << 2)
+#define HV_STIMER_AUTOENABLE           (1ULL << 3)
+#define HV_STIMER_SINT(config)         (__u8)(((config) >> 16) & 0x0F)
+
+#endif
index 38b4080b29c2683e47d2820cc5a43cf642dfcd61..74b5b3e518df9aee96092d90305924c70dab72d1 100644 (file)
@@ -34,6 +34,7 @@
 #include <asm/msr-index.h>
 #include <asm/asm.h>
 #include <asm/kvm_page_track.h>
+#include <asm/hyperv-tlfs.h>
 
 #define KVM_MAX_VCPUS 288
 #define KVM_SOFT_MAX_VCPUS 240
index 25283f7eb299e06ab703c11f7a2f95c0425f6a95..044323a59354ab5d423f4e143ac7eb9bc37959ec 100644 (file)
@@ -6,7 +6,7 @@
 #include <linux/atomic.h>
 #include <linux/nmi.h>
 #include <asm/io.h>
-#include <asm/hyperv.h>
+#include <asm/hyperv-tlfs.h>
 #include <asm/nospec-branch.h>
 
 /*
diff --git a/arch/x86/include/uapi/asm/hyperv.h b/arch/x86/include/uapi/asm/hyperv.h
deleted file mode 100644 (file)
index 6285cf8..0000000
+++ /dev/null
@@ -1,425 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_X86_HYPERV_H
-#define _ASM_X86_HYPERV_H
-
-#include <linux/types.h>
-
-/*
- * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
- * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
- */
-#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS  0x40000000
-#define HYPERV_CPUID_INTERFACE                 0x40000001
-#define HYPERV_CPUID_VERSION                   0x40000002
-#define HYPERV_CPUID_FEATURES                  0x40000003
-#define HYPERV_CPUID_ENLIGHTMENT_INFO          0x40000004
-#define HYPERV_CPUID_IMPLEMENT_LIMITS          0x40000005
-
-#define HYPERV_HYPERVISOR_PRESENT_BIT          0x80000000
-#define HYPERV_CPUID_MIN                       0x40000005
-#define HYPERV_CPUID_MAX                       0x4000ffff
-
-/*
- * Feature identification. EAX indicates which features are available
- * to the partition based upon the current partition privileges.
- */
-
-/* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
-#define HV_X64_MSR_VP_RUNTIME_AVAILABLE                (1 << 0)
-/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
-#define HV_X64_MSR_TIME_REF_COUNT_AVAILABLE    (1 << 1)
-/* Partition reference TSC MSR is available */
-#define HV_X64_MSR_REFERENCE_TSC_AVAILABLE              (1 << 9)
-
-/* A partition's reference time stamp counter (TSC) page */
-#define HV_X64_MSR_REFERENCE_TSC               0x40000021
-
-/*
- * There is a single feature flag that signifies if the partition has access
- * to MSRs with local APIC and TSC frequencies.
- */
-#define HV_X64_ACCESS_FREQUENCY_MSRS           (1 << 11)
-
-/* AccessReenlightenmentControls privilege */
-#define HV_X64_ACCESS_REENLIGHTENMENT          BIT(13)
-
-/*
- * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
- * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
- */
-#define HV_X64_MSR_SYNIC_AVAILABLE             (1 << 2)
-/*
- * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
- * HV_X64_MSR_STIMER3_COUNT) available
- */
-#define HV_X64_MSR_SYNTIMER_AVAILABLE          (1 << 3)
-/*
- * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
- * are available
- */
-#define HV_X64_MSR_APIC_ACCESS_AVAILABLE       (1 << 4)
-/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
-#define HV_X64_MSR_HYPERCALL_AVAILABLE         (1 << 5)
-/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
-#define HV_X64_MSR_VP_INDEX_AVAILABLE          (1 << 6)
-/* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
-#define HV_X64_MSR_RESET_AVAILABLE             (1 << 7)
- /*
-  * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
-  * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
-  * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
-  */
-#define HV_X64_MSR_STAT_PAGES_AVAILABLE                (1 << 8)
-
-/* Frequency MSRs available */
-#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE    (1 << 8)
-
-/* Crash MSR available */
-#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
-
-/*
- * Feature identification: EBX indicates which flags were specified at
- * partition creation. The format is the same as the partition creation
- * flag structure defined in section Partition Creation Flags.
- */
-#define HV_X64_CREATE_PARTITIONS               (1 << 0)
-#define HV_X64_ACCESS_PARTITION_ID             (1 << 1)
-#define HV_X64_ACCESS_MEMORY_POOL              (1 << 2)
-#define HV_X64_ADJUST_MESSAGE_BUFFERS          (1 << 3)
-#define HV_X64_POST_MESSAGES                   (1 << 4)
-#define HV_X64_SIGNAL_EVENTS                   (1 << 5)
-#define HV_X64_CREATE_PORT                     (1 << 6)
-#define HV_X64_CONNECT_PORT                    (1 << 7)
-#define HV_X64_ACCESS_STATS                    (1 << 8)
-#define HV_X64_DEBUGGING                       (1 << 11)
-#define HV_X64_CPU_POWER_MANAGEMENT            (1 << 12)
-#define HV_X64_CONFIGURE_PROFILER              (1 << 13)
-
-/*
- * Feature identification. EDX indicates which miscellaneous features
- * are available to the partition.
- */
-/* The MWAIT instruction is available (per section MONITOR / MWAIT) */
-#define HV_X64_MWAIT_AVAILABLE                         (1 << 0)
-/* Guest debugging support is available */
-#define HV_X64_GUEST_DEBUGGING_AVAILABLE               (1 << 1)
-/* Performance Monitor support is available*/
-#define HV_X64_PERF_MONITOR_AVAILABLE                  (1 << 2)
-/* Support for physical CPU dynamic partitioning events is available*/
-#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE      (1 << 3)
-/*
- * Support for passing hypercall input parameter block via XMM
- * registers is available
- */
-#define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE          (1 << 4)
-/* Support for a virtual guest idle state is available */
-#define HV_X64_GUEST_IDLE_STATE_AVAILABLE              (1 << 5)
-/* Guest crash data handler available */
-#define HV_X64_GUEST_CRASH_MSR_AVAILABLE               (1 << 10)
-
-/*
- * Implementation recommendations. Indicates which behaviors the hypervisor
- * recommends the OS implement for optimal performance.
- */
- /*
-  * Recommend using hypercall for address space switches rather
-  * than MOV to CR3 instruction
-  */
-#define HV_X64_AS_SWITCH_RECOMMENDED           (1 << 0)
-/* Recommend using hypercall for local TLB flushes rather
- * than INVLPG or MOV to CR3 instructions */
-#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED     (1 << 1)
-/*
- * Recommend using hypercall for remote TLB flushes rather
- * than inter-processor interrupts
- */
-#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED    (1 << 2)
-/*
- * Recommend using MSRs for accessing APIC registers
- * EOI, ICR and TPR rather than their memory-mapped counterparts
- */
-#define HV_X64_APIC_ACCESS_RECOMMENDED         (1 << 3)
-/* Recommend using the hypervisor-provided MSR to initiate a system RESET */
-#define HV_X64_SYSTEM_RESET_RECOMMENDED                (1 << 4)
-/*
- * Recommend using relaxed timing for this partition. If used,
- * the VM should disable any watchdog timeouts that rely on the
- * timely delivery of external interrupts
- */
-#define HV_X64_RELAXED_TIMING_RECOMMENDED      (1 << 5)
-
-/*
- * Virtual APIC support
- */
-#define HV_X64_DEPRECATING_AEOI_RECOMMENDED    (1 << 9)
-
-/* Recommend using the newer ExProcessorMasks interface */
-#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED  (1 << 11)
-
-/*
- * Crash notification flag.
- */
-#define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63)
-
-/* MSR used to identify the guest OS. */
-#define HV_X64_MSR_GUEST_OS_ID                 0x40000000
-
-/* MSR used to setup pages used to communicate with the hypervisor. */
-#define HV_X64_MSR_HYPERCALL                   0x40000001
-
-/* MSR used to provide vcpu index */
-#define HV_X64_MSR_VP_INDEX                    0x40000002
-
-/* MSR used to reset the guest OS. */
-#define HV_X64_MSR_RESET                       0x40000003
-
-/* MSR used to provide vcpu runtime in 100ns units */
-#define HV_X64_MSR_VP_RUNTIME                  0x40000010
-
-/* MSR used to read the per-partition time reference counter */
-#define HV_X64_MSR_TIME_REF_COUNT              0x40000020
-
-/* MSR used to retrieve the TSC frequency */
-#define HV_X64_MSR_TSC_FREQUENCY               0x40000022
-
-/* MSR used to retrieve the local APIC timer frequency */
-#define HV_X64_MSR_APIC_FREQUENCY              0x40000023
-
-/* Define the virtual APIC registers */
-#define HV_X64_MSR_EOI                         0x40000070
-#define HV_X64_MSR_ICR                         0x40000071
-#define HV_X64_MSR_TPR                         0x40000072
-#define HV_X64_MSR_APIC_ASSIST_PAGE            0x40000073
-
-/* Define synthetic interrupt controller model specific registers. */
-#define HV_X64_MSR_SCONTROL                    0x40000080
-#define HV_X64_MSR_SVERSION                    0x40000081
-#define HV_X64_MSR_SIEFP                       0x40000082
-#define HV_X64_MSR_SIMP                                0x40000083
-#define HV_X64_MSR_EOM                         0x40000084
-#define HV_X64_MSR_SINT0                       0x40000090
-#define HV_X64_MSR_SINT1                       0x40000091
-#define HV_X64_MSR_SINT2                       0x40000092
-#define HV_X64_MSR_SINT3                       0x40000093
-#define HV_X64_MSR_SINT4                       0x40000094
-#define HV_X64_MSR_SINT5                       0x40000095
-#define HV_X64_MSR_SINT6                       0x40000096
-#define HV_X64_MSR_SINT7                       0x40000097
-#define HV_X64_MSR_SINT8                       0x40000098
-#define HV_X64_MSR_SINT9                       0x40000099
-#define HV_X64_MSR_SINT10                      0x4000009A
-#define HV_X64_MSR_SINT11                      0x4000009B
-#define HV_X64_MSR_SINT12                      0x4000009C
-#define HV_X64_MSR_SINT13                      0x4000009D
-#define HV_X64_MSR_SINT14                      0x4000009E
-#define HV_X64_MSR_SINT15                      0x4000009F
-
-/*
- * Synthetic Timer MSRs. Four timers per vcpu.
- */
-#define HV_X64_MSR_STIMER0_CONFIG              0x400000B0
-#define HV_X64_MSR_STIMER0_COUNT               0x400000B1
-#define HV_X64_MSR_STIMER1_CONFIG              0x400000B2
-#define HV_X64_MSR_STIMER1_COUNT               0x400000B3
-#define HV_X64_MSR_STIMER2_CONFIG              0x400000B4
-#define HV_X64_MSR_STIMER2_COUNT               0x400000B5
-#define HV_X64_MSR_STIMER3_CONFIG              0x400000B6
-#define HV_X64_MSR_STIMER3_COUNT               0x400000B7
-
-/* Hyper-V guest crash notification MSR's */
-#define HV_X64_MSR_CRASH_P0                    0x40000100
-#define HV_X64_MSR_CRASH_P1                    0x40000101
-#define HV_X64_MSR_CRASH_P2                    0x40000102
-#define HV_X64_MSR_CRASH_P3                    0x40000103
-#define HV_X64_MSR_CRASH_P4                    0x40000104
-#define HV_X64_MSR_CRASH_CTL                   0x40000105
-#define HV_X64_MSR_CRASH_CTL_NOTIFY            (1ULL << 63)
-#define HV_X64_MSR_CRASH_PARAMS                \
-               (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
-
-/* TSC emulation after migration */
-#define HV_X64_MSR_REENLIGHTENMENT_CONTROL     0x40000106
-
-struct hv_reenlightenment_control {
-       __u64 vector:8;
-       __u64 reserved1:8;
-       __u64 enabled:1;
-       __u64 reserved2:15;
-       __u64 target_vp:32;
-};
-
-#define HV_X64_MSR_TSC_EMULATION_CONTROL       0x40000107
-#define HV_X64_MSR_TSC_EMULATION_STATUS                0x40000108
-
-struct hv_tsc_emulation_control {
-       __u64 enabled:1;
-       __u64 reserved:63;
-};
-
-struct hv_tsc_emulation_status {
-       __u64 inprogress:1;
-       __u64 reserved:63;
-};
-
-#define HV_X64_MSR_HYPERCALL_ENABLE            0x00000001
-#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT        12
-#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \
-               (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
-
-/* Declare the various hypercall operations. */
-#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE     0x0002
-#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST      0x0003
-#define HVCALL_NOTIFY_LONG_SPIN_WAIT           0x0008
-#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX  0x0013
-#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX   0x0014
-#define HVCALL_POST_MESSAGE                    0x005c
-#define HVCALL_SIGNAL_EVENT                    0x005d
-
-#define HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE             0x00000001
-#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT      12
-#define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK       \
-               (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
-
-#define HV_X64_MSR_TSC_REFERENCE_ENABLE                0x00000001
-#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12
-
-#define HV_PROCESSOR_POWER_STATE_C0            0
-#define HV_PROCESSOR_POWER_STATE_C1            1
-#define HV_PROCESSOR_POWER_STATE_C2            2
-#define HV_PROCESSOR_POWER_STATE_C3            3
-
-#define HV_FLUSH_ALL_PROCESSORS                        BIT(0)
-#define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES    BIT(1)
-#define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY      BIT(2)
-#define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT     BIT(3)
-
-enum HV_GENERIC_SET_FORMAT {
-       HV_GENERIC_SET_SPARCE_4K,
-       HV_GENERIC_SET_ALL,
-};
-
-/* hypercall status code */
-#define HV_STATUS_SUCCESS                      0
-#define HV_STATUS_INVALID_HYPERCALL_CODE       2
-#define HV_STATUS_INVALID_HYPERCALL_INPUT      3
-#define HV_STATUS_INVALID_ALIGNMENT            4
-#define HV_STATUS_INVALID_PARAMETER            5
-#define HV_STATUS_INSUFFICIENT_MEMORY          11
-#define HV_STATUS_INVALID_PORT_ID              17
-#define HV_STATUS_INVALID_CONNECTION_ID                18
-#define HV_STATUS_INSUFFICIENT_BUFFERS         19
-
-typedef struct _HV_REFERENCE_TSC_PAGE {
-       __u32 tsc_sequence;
-       __u32 res1;
-       __u64 tsc_scale;
-       __s64 tsc_offset;
-} HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
-
-/* Define the number of synthetic interrupt sources. */
-#define HV_SYNIC_SINT_COUNT            (16)
-/* Define the expected SynIC version. */
-#define HV_SYNIC_VERSION_1             (0x1)
-/* Valid SynIC vectors are 16-255. */
-#define HV_SYNIC_FIRST_VALID_VECTOR    (16)
-
-#define HV_SYNIC_CONTROL_ENABLE                (1ULL << 0)
-#define HV_SYNIC_SIMP_ENABLE           (1ULL << 0)
-#define HV_SYNIC_SIEFP_ENABLE          (1ULL << 0)
-#define HV_SYNIC_SINT_MASKED           (1ULL << 16)
-#define HV_SYNIC_SINT_AUTO_EOI         (1ULL << 17)
-#define HV_SYNIC_SINT_VECTOR_MASK      (0xFF)
-
-#define HV_SYNIC_STIMER_COUNT          (4)
-
-/* Define synthetic interrupt controller message constants. */
-#define HV_MESSAGE_SIZE                        (256)
-#define HV_MESSAGE_PAYLOAD_BYTE_COUNT  (240)
-#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30)
-
-/* Define hypervisor message types. */
-enum hv_message_type {
-       HVMSG_NONE                      = 0x00000000,
-
-       /* Memory access messages. */
-       HVMSG_UNMAPPED_GPA              = 0x80000000,
-       HVMSG_GPA_INTERCEPT             = 0x80000001,
-
-       /* Timer notification messages. */
-       HVMSG_TIMER_EXPIRED                     = 0x80000010,
-
-       /* Error messages. */
-       HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
-       HVMSG_UNRECOVERABLE_EXCEPTION   = 0x80000021,
-       HVMSG_UNSUPPORTED_FEATURE               = 0x80000022,
-
-       /* Trace buffer complete messages. */
-       HVMSG_EVENTLOG_BUFFERCOMPLETE   = 0x80000040,
-
-       /* Platform-specific processor intercept messages. */
-       HVMSG_X64_IOPORT_INTERCEPT              = 0x80010000,
-       HVMSG_X64_MSR_INTERCEPT         = 0x80010001,
-       HVMSG_X64_CPUID_INTERCEPT               = 0x80010002,
-       HVMSG_X64_EXCEPTION_INTERCEPT   = 0x80010003,
-       HVMSG_X64_APIC_EOI                      = 0x80010004,
-       HVMSG_X64_LEGACY_FP_ERROR               = 0x80010005
-};
-
-/* Define synthetic interrupt controller message flags. */
-union hv_message_flags {
-       __u8 asu8;
-       struct {
-               __u8 msg_pending:1;
-               __u8 reserved:7;
-       };
-};
-
-/* Define port identifier type. */
-union hv_port_id {
-       __u32 asu32;
-       struct {
-               __u32 id:24;
-               __u32 reserved:8;
-       } u;
-};
-
-/* Define synthetic interrupt controller message header. */
-struct hv_message_header {
-       __u32 message_type;
-       __u8 payload_size;
-       union hv_message_flags message_flags;
-       __u8 reserved[2];
-       union {
-               __u64 sender;
-               union hv_port_id port;
-       };
-};
-
-/* Define synthetic interrupt controller message format. */
-struct hv_message {
-       struct hv_message_header header;
-       union {
-               __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
-       } u;
-};
-
-/* Define the synthetic interrupt message page layout. */
-struct hv_message_page {
-       struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
-};
-
-/* Define timer message payload structure. */
-struct hv_timer_message_payload {
-       __u32 timer_index;
-       __u32 reserved;
-       __u64 expiration_time;  /* When the timer expired */
-       __u64 delivery_time;    /* When the message was delivered */
-};
-
-#define HV_STIMER_ENABLE               (1ULL << 0)
-#define HV_STIMER_PERIODIC             (1ULL << 1)
-#define HV_STIMER_LAZY                 (1ULL << 2)
-#define HV_STIMER_AUTOENABLE           (1ULL << 3)
-#define HV_STIMER_SINT(config)         (__u8)(((config) >> 16) & 0x0F)
-
-#endif
index 68a41b6ba3da3ff7d46834f812fdd9087a7abc80..4c851ebb3cebd4654f9dabed1e9c19520b072c0d 100644 (file)
@@ -3,7 +3,6 @@
 #define _UAPI_ASM_X86_KVM_PARA_H
 
 #include <linux/types.h>
-#include <asm/hyperv.h>
 
 /* This CPUID returns the signature 'KVMKVMKVM' in ebx, ecx, and edx.  It
  * should be used to determine that a VM is running under KVM.
index 9340f41ce8d3d374ff4453638d88759ec5f72064..04f760432a175a5ce711ca086fa8b5ddf80e19fd 100644 (file)
@@ -22,7 +22,7 @@
 #include <linux/kexec.h>
 #include <asm/processor.h>
 #include <asm/hypervisor.h>
-#include <asm/hyperv.h>
+#include <asm/hyperv-tlfs.h>
 #include <asm/mshyperv.h>
 #include <asm/desc.h>
 #include <asm/irq_regs.h>
index 447371f4de5675d8b786a99d298d583f657dc5bd..72855182b1919d6fa609171dac759cb444383fce 100644 (file)
@@ -31,7 +31,6 @@
 #include <linux/vmalloc.h>
 #include <linux/hyperv.h>
 #include <linux/export.h>
-#include <asm/hyperv.h>
 #include <asm/mshyperv.h>
 
 #include "hyperv_vmbus.h"
index fe96aab9e794fac85b919757c57751bed6cab9c5..45f3694bbb76a4e5a175fc8e3fbf237c883a5c23 100644 (file)
@@ -29,7 +29,6 @@
 #include <linux/version.h>
 #include <linux/interrupt.h>
 #include <linux/clockchips.h>
-#include <asm/hyperv.h>
 #include <asm/mshyperv.h>
 #include "hyperv_vmbus.h"
 
index 22300ec7b5567478bbeb607b84a0c6f6cd94c785..500f805a6ef224b5cb9327d50b81579211d8a5b3 100644 (file)
@@ -27,6 +27,7 @@
 
 #include <linux/list.h>
 #include <asm/sync_bitops.h>
+#include <asm/hyperv-tlfs.h>
 #include <linux/atomic.h>
 #include <linux/hyperv.h>
 #include <linux/interrupt.h>
index bc65c4d79c1f1a2fd0d5b0538fa513f0ea2263f4..b10fe26c48917983951e443d83584cd49295853d 100644 (file)
@@ -36,7 +36,6 @@
 #include <linux/cpu.h>
 #include <linux/sched/task_stack.h>
 
-#include <asm/hyperv.h>
 #include <asm/mshyperv.h>
 #include <linux/notifier.h>
 #include <linux/ptrace.h>
index 93bd6fcd6e6217144496feef423b491151865707..eed8b33b0173737d965a03969153e0d79209197d 100644 (file)
@@ -26,7 +26,6 @@
 #define _HYPERV_H
 
 #include <uapi/linux/hyperv.h>
-#include <uapi/asm/hyperv.h>
 
 #include <linux/types.h>
 #include <linux/scatterlist.h>