drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based

On Xe_HP the fusing register is renamed and changed to have the "enable"
semantics, but otherwise remains compatible (mmio address, bitmask
ranges) with older platforms.

To simplify things we do not add a new register definition but just stop
inverting the fusing masks before processing them.

Bspec: 52615
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210721223043.834562-6-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 9c8cba1c6cd1da403cb513f3701d899c0af72839..4168b9fc59e16ff2b64ec77b1b38f11331d3a1cd 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -486,7 +486,14 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
        if (GRAPHICS_VER(i915) < 11)
                return info->engine_mask;
 
-       media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
+       /*
+        * On newer platforms the fusing register is called 'enable' and has
+        * enable semantics, while on older platforms it is called 'disable'
+        * and bits have disable semantices.
+        */
+       media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
+       if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
+               media_fuse = ~media_fuse;
 
        vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
        vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>