net: macb: Disable PCS auto-negotiation for SGMII fixed-link mode

When using a fixed-link configuration in SGMII mode, it's not really
sensible to have auto-negotiation enabled since the link settings are
fixed by definition. In other configurations, such as an SGMII
connection to a PHY, it should generally be enabled.

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
index d8c68906525a9a3e6affd1e6c3558d8dd65b575b..d8d87213697cdedd0d92c417147a291bb793fa34 100644 (file)
--- a/drivers/net/ethernet/cadence/macb.h
+++ b/drivers/net/ethernet/cadence/macb.h
@@ -159,6 +159,16 @@
 #define GEM_PEFTN              0x01f4 /* PTP Peer Event Frame Tx Ns */
 #define GEM_PEFRSL             0x01f8 /* PTP Peer Event Frame Rx Sec Low */
 #define GEM_PEFRN              0x01fc /* PTP Peer Event Frame Rx Ns */
+#define GEM_PCSCNTRL           0x0200 /* PCS Control */
+#define GEM_PCSSTS             0x0204 /* PCS Status */
+#define GEM_PCSPHYTOPID                0x0208 /* PCS PHY Top ID */
+#define GEM_PCSPHYBOTID                0x020c /* PCS PHY Bottom ID */
+#define GEM_PCSANADV           0x0210 /* PCS AN Advertisement */
+#define GEM_PCSANLPBASE                0x0214 /* PCS AN Link Partner Base */
+#define GEM_PCSANEXP           0x0218 /* PCS AN Expansion */
+#define GEM_PCSANNPTX          0x021c /* PCS AN Next Page TX */
+#define GEM_PCSANNPLP          0x0220 /* PCS AN Next Page LP */
+#define GEM_PCSANEXTSTS                0x023c /* PCS AN Extended Status */
 #define GEM_DCFG1              0x0280 /* Design Config 1 */
 #define GEM_DCFG2              0x0284 /* Design Config 2 */
 #define GEM_DCFG3              0x0288 /* Design Config 3 */
@@ -478,6 +488,10 @@
 #define GEM_HS_MAC_SPEED_OFFSET                        0
 #define GEM_HS_MAC_SPEED_SIZE                  3
 
+/* Bitfields in PCSCNTRL */
+#define GEM_PCSAUTONEG_OFFSET                  12
+#define GEM_PCSAUTONEG_SIZE                    1
+
 /* Bitfields in DCFG1. */
 #define GEM_IRQCOR_OFFSET                      23
 #define GEM_IRQCOR_SIZE                                1

diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index ca72a16c8da3da6dd0273522ee27fd083a59c6b6..e7c123aadf565f79ca60390b316270105ccb2c29 100644 (file)
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -694,6 +694,22 @@ static void macb_mac_config(struct phylink_config *config, unsigned int mode,
        if (old_ncr ^ ncr)
                macb_or_gem_writel(bp, NCR, ncr);
 
+       /* Disable AN for SGMII fixed link configuration, enable otherwise.
+        * Must be written after PCSSEL is set in NCFGR,
+        * otherwise writes will not take effect.
+        */
+       if (macb_is_gem(bp) && state->interface == PHY_INTERFACE_MODE_SGMII) {
+               u32 pcsctrl, old_pcsctrl;
+
+               old_pcsctrl = gem_readl(bp, PCSCNTRL);
+               if (mode == MLO_AN_FIXED)
+                       pcsctrl = old_pcsctrl & ~GEM_BIT(PCSAUTONEG);
+               else
+                       pcsctrl = old_pcsctrl | GEM_BIT(PCSAUTONEG);
+               if (old_pcsctrl != pcsctrl)
+                       gem_writel(bp, PCSCNTRL, pcsctrl);
+       }
+
        spin_unlock_irqrestore(&bp->lock, flags);
 }