drm/i915/icl: Set TBT IO in Aux transaction

For a TBT sequence, we need to set the IO type to TBT
in  DDI_AUX_CTL.

v2: Avoid duplications.(Paulo)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1532648115-29795-2-git-send-email-anusha.srivatsa@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5530c470f30d41c482f5a2f8fff993659227c0ed..7bdc214ffb6e2dfcacefe2ff021836fc9d4ef359 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5558,6 +5558,7 @@ enum {
 #define   DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL   (1 << 14)
 #define   DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL    (1 << 13)
 #define   DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL   (1 << 12)
+#define   DP_AUX_CH_CTL_TBT_IO                 (1 << 11)
 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
 #define   DP_AUX_CH_CTL_SYNC_PULSE_SKL(c)   ((c) - 1)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ac59590b281bcc1860a0a2d7f3d01066064ed6e5..8e0e14ba534fa167dccf60ff3532c02ab3c44540 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1208,15 +1208,23 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
                                      int send_bytes,
                                      uint32_t unused)
 {
-       return DP_AUX_CH_CTL_SEND_BUSY |
-              DP_AUX_CH_CTL_DONE |
-              DP_AUX_CH_CTL_INTERRUPT |
-              DP_AUX_CH_CTL_TIME_OUT_ERROR |
-              DP_AUX_CH_CTL_TIME_OUT_MAX |
-              DP_AUX_CH_CTL_RECEIVE_ERROR |
-              (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
-              DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
-              DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
+       struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+       uint32_t ret;
+
+       ret = DP_AUX_CH_CTL_SEND_BUSY |
+             DP_AUX_CH_CTL_DONE |
+             DP_AUX_CH_CTL_INTERRUPT |
+             DP_AUX_CH_CTL_TIME_OUT_ERROR |
+             DP_AUX_CH_CTL_TIME_OUT_MAX |
+             DP_AUX_CH_CTL_RECEIVE_ERROR |
+             (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+             DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
+             DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
+
+       if (intel_dig_port->tc_type == TC_PORT_TBT)
+               ret |= DP_AUX_CH_CTL_TBT_IO;
+
+       return ret;
 }
 
 static int