]> git.baikalelectronics.ru Git - kernel.git/commitdiff
drm/i915/guc: Handle engine reset failure notification
authorMatthew Brost <matthew.brost@intel.com>
Tue, 27 Jul 2021 00:23:28 +0000 (17:23 -0700)
committerJohn Harrison <John.C.Harrison@Intel.com>
Wed, 28 Jul 2021 00:31:52 +0000 (17:31 -0700)
GuC will notify the driver, via G2H, if it fails to
reset an engine. We recover by resorting to a full GPU
reset.

v2:
 (John Harrison):
  - s/drm_dbg/drm_err

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Fernando Pacheco <fernando.pacheco@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210727002348.97202-14-matthew.brost@intel.com
drivers/gpu/drm/i915/gt/uc/intel_guc.h
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

index c79da154c16ddcca1d810598a7a87a6b458d377c..9c8d53a32e0d5d8fd878588f07de7c4d99800237 100644 (file)
@@ -271,6 +271,8 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
                                     const u32 *msg, u32 len);
 int intel_guc_context_reset_process_msg(struct intel_guc *guc,
                                        const u32 *msg, u32 len);
+int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
+                                        const u32 *msg, u32 len);
 
 void intel_guc_submission_reset_prepare(struct intel_guc *guc);
 void intel_guc_submission_reset(struct intel_guc *guc, bool stalled);
index 231a428876758fc5b33c62398e8d7b705d1b27b9..18917b443f0594dc7d07225e8341ad145688c43d 100644 (file)
@@ -987,6 +987,9 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
        case INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION:
                ret = intel_guc_context_reset_process_msg(guc, payload, len);
                break;
+       case INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION:
+               ret = intel_guc_engine_failure_process_msg(guc, payload, len);
+               break;
        default:
                ret = -EOPNOTSUPP;
                break;
index 7be84b0761b526371c8892a3f0fdb7c1278d18f4..d76494e3e271e4b954e088e8b908fcd60ef3f93e 100644 (file)
@@ -2237,6 +2237,49 @@ int intel_guc_context_reset_process_msg(struct intel_guc *guc,
        return 0;
 }
 
+static struct intel_engine_cs *
+guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance)
+{
+       struct intel_gt *gt = guc_to_gt(guc);
+       u8 engine_class = guc_class_to_engine_class(guc_class);
+
+       /* Class index is checked in class converter */
+       GEM_BUG_ON(instance > MAX_ENGINE_INSTANCE);
+
+       return gt->engine_class[engine_class][instance];
+}
+
+int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
+                                        const u32 *msg, u32 len)
+{
+       struct intel_engine_cs *engine;
+       u8 guc_class, instance;
+       u32 reason;
+
+       if (unlikely(len != 3)) {
+               drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
+               return -EPROTO;
+       }
+
+       guc_class = msg[0];
+       instance = msg[1];
+       reason = msg[2];
+
+       engine = guc_lookup_engine(guc, guc_class, instance);
+       if (unlikely(!engine)) {
+               drm_err(&guc_to_gt(guc)->i915->drm,
+                       "Invalid engine %d:%d", guc_class, instance);
+               return -EPROTO;
+       }
+
+       intel_gt_handle_error(guc_to_gt(guc), engine->mask,
+                             I915_ERROR_CAPTURE,
+                             "GuC failed to reset %s (reason=0x%08x)\n",
+                             engine->name, reason);
+
+       return 0;
+}
+
 void intel_guc_submission_print_info(struct intel_guc *guc,
                                     struct drm_printer *p)
 {