riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC

Link: https://lore.kernel.org/r/20210504105940.100004-7-greentime.hu@sifive.com
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>

diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
index eeb4f8c3e0e72340372b8ff745cabdebf65982e1..8eef82e4199f572170bfbf48633945f2773a1f6c 100644 (file)
--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -159,6 +159,7 @@
                        reg = <0x0 0x10000000 0x0 0x1000>;
                        clocks = <&hfclk>, <&rtcclk>;
                        #clock-cells = <1>;
+                       #reset-cells = <1>;
                };
                uart0: serial@10010000 {
                        compatible = "sifive,fu740-c000-uart", "sifive,uart0";
@@ -289,5 +290,37 @@
                        clocks = <&prci PRCI_CLK_PCLK>;
                        status = "disabled";
                };
+               pcie@e00000000 {
+                       compatible = "sifive,fu740-pcie";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       reg = <0xe 0x00000000 0x0 0x80000000>,
+                             <0xd 0xf0000000 0x0 0x10000000>,
+                             <0x0 0x100d0000 0x0 0x1000>;
+                       reg-names = "dbi", "config", "mgmt";
+                       device_type = "pci";
+                       dma-coherent;
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000>,      /* I/O */
+                                <0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000>,    /* mem */
+                                <0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000>,    /* mem */
+                                <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */
+                       num-lanes = <0x8>;
+                       interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
+                       interrupt-names = "msi", "inta", "intb", "intc", "intd";
+                       interrupt-parent = <&plic0>;
+                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                       interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
+                                       <0x0 0x0 0x0 0x2 &plic0 58>,
+                                       <0x0 0x0 0x0 0x3 &plic0 59>,
+                                       <0x0 0x0 0x0 0x4 &plic0 60>;
+                       clock-names = "pcie_aux";
+                       clocks = <&prci PRCI_CLK_PCIE_AUX>;
+                       pwren-gpios = <&gpio 5 0>;
+                       reset-gpios = <&gpio 8 0>;
+                       resets = <&prci 4>;
+                       status = "okay";
+               };
        };
 };