drm/i915: Add workaround numbers to GEN7_COMMON_SLICE_CHICKEN1 whitelisting

Those two workarounds needs to be implemented in UMD, KMD only needs
to whitelist the registers, so here only adding the workaround number
to facilitate future workaroud table checks.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211119140931.32791-2-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index cd2935b9e7c813310bafe3a58d5043c3fd0f7563..c3211325c2d3e8eaa28af9ebec20a0defb668bc8 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1869,7 +1869,11 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
                                  RING_FORCE_TO_NONPRIV_ACCESS_RD |
                                  RING_FORCE_TO_NONPRIV_RANGE_4);
 
-               /* Wa_1808121037:tgl */
+               /*
+                * Wa_1808121037:tgl
+                * Wa_14012131227:dg1
+                * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p
+                */
                whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
 
                /* Wa_1806527549:tgl */