SCDC Helper Functions Reference
===============================
-.. kernel-doc:: drivers/gpu/drm/drm_scdc_helper.c
+.. kernel-doc:: drivers/gpu/drm/display/drm_scdc_helper.c
:doc: scdc helpers
-.. kernel-doc:: include/drm/drm_scdc_helper.h
+.. kernel-doc:: include/drm/display/drm_scdc_helper.h
:internal:
-.. kernel-doc:: drivers/gpu/drm/drm_scdc_helper.c
+.. kernel-doc:: drivers/gpu/drm/display/drm_scdc_helper.c
:export:
HDMI Infoframes Helper Reference
drm_plane_helper.o drm_atomic_helper.o \
drm_kms_helper_common.o \
drm_simple_kms_helper.o drm_modeset_helper.o \
- drm_scdc_helper.o drm_gem_atomic_helper.o \
+ drm_gem_atomic_helper.o \
drm_gem_framebuffer_helper.o \
drm_atomic_state_helper.o drm_damage_helper.o \
drm_format_helper.o drm_self_refresh_helper.o drm_rect.o
#include <drm/bridge/dw_hdmi.h>
#include <drm/display/drm_hdmi_helper.h>
+#include <drm/display/drm_scdc_helper.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
#include <drm/drm_of.h>
#include <drm/drm_print.h>
#include <drm/drm_probe_helper.h>
-#include <drm/drm_scdc_helper.h>
#include "dw-hdmi-audio.h"
#include "dw-hdmi-cec.h"
drm_dp_mst_topology.o \
drm_dsc_helper.o
drm_display_helper-$(CONFIG_DRM_DISPLAY_HDCP_HELPER) += drm_hdcp_helper.o
-drm_display_helper-$(CONFIG_DRM_DISPLAY_HDMI_HELPER) += drm_hdmi_helper.o
+drm_display_helper-$(CONFIG_DRM_DISPLAY_HDMI_HELPER) += drm_hdmi_helper.o \
+ drm_scdc_helper.o
drm_display_helper-$(CONFIG_DRM_DP_AUX_CHARDEV) += drm_dp_aux_dev.o
drm_display_helper-$(CONFIG_DRM_DP_CEC) += drm_dp_cec.o
--- /dev/null
+/*
+ * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+
+#include <drm/display/drm_scdc_helper.h>
+#include <drm/drm_print.h>
+
+/**
+ * DOC: scdc helpers
+ *
+ * Status and Control Data Channel (SCDC) is a mechanism introduced by the
+ * HDMI 2.0 specification. It is a point-to-point protocol that allows the
+ * HDMI source and HDMI sink to exchange data. The same I2C interface that
+ * is used to access EDID serves as the transport mechanism for SCDC.
+ */
+
+#define SCDC_I2C_SLAVE_ADDRESS 0x54
+
+/**
+ * drm_scdc_read - read a block of data from SCDC
+ * @adapter: I2C controller
+ * @offset: start offset of block to read
+ * @buffer: return location for the block to read
+ * @size: size of the block to read
+ *
+ * Reads a block of data from SCDC, starting at a given offset.
+ *
+ * Returns:
+ * 0 on success, negative error code on failure.
+ */
+ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,
+ size_t size)
+{
+ int ret;
+ struct i2c_msg msgs[2] = {
+ {
+ .addr = SCDC_I2C_SLAVE_ADDRESS,
+ .flags = 0,
+ .len = 1,
+ .buf = &offset,
+ }, {
+ .addr = SCDC_I2C_SLAVE_ADDRESS,
+ .flags = I2C_M_RD,
+ .len = size,
+ .buf = buffer,
+ }
+ };
+
+ ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
+ if (ret < 0)
+ return ret;
+ if (ret != ARRAY_SIZE(msgs))
+ return -EPROTO;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_scdc_read);
+
+/**
+ * drm_scdc_write - write a block of data to SCDC
+ * @adapter: I2C controller
+ * @offset: start offset of block to write
+ * @buffer: block of data to write
+ * @size: size of the block to write
+ *
+ * Writes a block of data to SCDC, starting at a given offset.
+ *
+ * Returns:
+ * 0 on success, negative error code on failure.
+ */
+ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
+ const void *buffer, size_t size)
+{
+ struct i2c_msg msg = {
+ .addr = SCDC_I2C_SLAVE_ADDRESS,
+ .flags = 0,
+ .len = 1 + size,
+ .buf = NULL,
+ };
+ void *data;
+ int err;
+
+ data = kmalloc(1 + size, GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ msg.buf = data;
+
+ memcpy(data, &offset, sizeof(offset));
+ memcpy(data + 1, buffer, size);
+
+ err = i2c_transfer(adapter, &msg, 1);
+
+ kfree(data);
+
+ if (err < 0)
+ return err;
+ if (err != 1)
+ return -EPROTO;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_scdc_write);
+
+/**
+ * drm_scdc_get_scrambling_status - what is status of scrambling?
+ * @adapter: I2C adapter for DDC channel
+ *
+ * Reads the scrambler status over SCDC, and checks the
+ * scrambling status.
+ *
+ * Returns:
+ * True if the scrambling is enabled, false otherwise.
+ */
+bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter)
+{
+ u8 status;
+ int ret;
+
+ ret = drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, &status);
+ if (ret < 0) {
+ DRM_DEBUG_KMS("Failed to read scrambling status: %d\n", ret);
+ return false;
+ }
+
+ return status & SCDC_SCRAMBLING_STATUS;
+}
+EXPORT_SYMBOL(drm_scdc_get_scrambling_status);
+
+/**
+ * drm_scdc_set_scrambling - enable scrambling
+ * @adapter: I2C adapter for DDC channel
+ * @enable: bool to indicate if scrambling is to be enabled/disabled
+ *
+ * Writes the TMDS config register over SCDC channel, and:
+ * enables scrambling when enable = 1
+ * disables scrambling when enable = 0
+ *
+ * Returns:
+ * True if scrambling is set/reset successfully, false otherwise.
+ */
+bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable)
+{
+ u8 config;
+ int ret;
+
+ ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
+ if (ret < 0) {
+ DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret);
+ return false;
+ }
+
+ if (enable)
+ config |= SCDC_SCRAMBLING_ENABLE;
+ else
+ config &= ~SCDC_SCRAMBLING_ENABLE;
+
+ ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
+ if (ret < 0) {
+ DRM_DEBUG_KMS("Failed to enable scrambling: %d\n", ret);
+ return false;
+ }
+
+ return true;
+}
+EXPORT_SYMBOL(drm_scdc_set_scrambling);
+
+/**
+ * drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
+ * @adapter: I2C adapter for DDC channel
+ * @set: ret or reset the high clock ratio
+ *
+ *
+ * TMDS clock ratio calculations go like this:
+ * TMDS character = 10 bit TMDS encoded value
+ *
+ * TMDS character rate = The rate at which TMDS characters are
+ * transmitted (Mcsc)
+ *
+ * TMDS bit rate = 10x TMDS character rate
+ *
+ * As per the spec:
+ * TMDS clock rate for pixel clock < 340 MHz = 1x the character
+ * rate = 1/10 pixel clock rate
+ *
+ * TMDS clock rate for pixel clock > 340 MHz = 0.25x the character
+ * rate = 1/40 pixel clock rate
+ *
+ * Writes to the TMDS config register over SCDC channel, and:
+ * sets TMDS clock ratio to 1/40 when set = 1
+ *
+ * sets TMDS clock ratio to 1/10 when set = 0
+ *
+ * Returns:
+ * True if write is successful, false otherwise.
+ */
+bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set)
+{
+ u8 config;
+ int ret;
+
+ ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
+ if (ret < 0) {
+ DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret);
+ return false;
+ }
+
+ if (set)
+ config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
+ else
+ config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
+
+ ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
+ if (ret < 0) {
+ DRM_DEBUG_KMS("Failed to set TMDS clock ratio: %d\n", ret);
+ return false;
+ }
+
+ /*
+ * The spec says that a source should wait minimum 1ms and maximum
+ * 100ms after writing the TMDS config for clock ratio. Lets allow a
+ * wait of up to 2ms here.
+ */
+ usleep_range(1000, 2000);
+ return true;
+}
+EXPORT_SYMBOL(drm_scdc_set_high_tmds_clock_ratio);
#include <drm/drm_edid.h>
#include <drm/drm_encoder.h>
#include <drm/drm_print.h>
-#include <drm/drm_scdc_helper.h>
#include "drm_crtc_internal.h"
+++ /dev/null
-/*
- * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sub license,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <linux/slab.h>
-#include <linux/delay.h>
-
-#include <drm/drm_print.h>
-#include <drm/drm_scdc_helper.h>
-
-/**
- * DOC: scdc helpers
- *
- * Status and Control Data Channel (SCDC) is a mechanism introduced by the
- * HDMI 2.0 specification. It is a point-to-point protocol that allows the
- * HDMI source and HDMI sink to exchange data. The same I2C interface that
- * is used to access EDID serves as the transport mechanism for SCDC.
- */
-
-#define SCDC_I2C_SLAVE_ADDRESS 0x54
-
-/**
- * drm_scdc_read - read a block of data from SCDC
- * @adapter: I2C controller
- * @offset: start offset of block to read
- * @buffer: return location for the block to read
- * @size: size of the block to read
- *
- * Reads a block of data from SCDC, starting at a given offset.
- *
- * Returns:
- * 0 on success, negative error code on failure.
- */
-ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,
- size_t size)
-{
- int ret;
- struct i2c_msg msgs[2] = {
- {
- .addr = SCDC_I2C_SLAVE_ADDRESS,
- .flags = 0,
- .len = 1,
- .buf = &offset,
- }, {
- .addr = SCDC_I2C_SLAVE_ADDRESS,
- .flags = I2C_M_RD,
- .len = size,
- .buf = buffer,
- }
- };
-
- ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
- if (ret < 0)
- return ret;
- if (ret != ARRAY_SIZE(msgs))
- return -EPROTO;
-
- return 0;
-}
-EXPORT_SYMBOL(drm_scdc_read);
-
-/**
- * drm_scdc_write - write a block of data to SCDC
- * @adapter: I2C controller
- * @offset: start offset of block to write
- * @buffer: block of data to write
- * @size: size of the block to write
- *
- * Writes a block of data to SCDC, starting at a given offset.
- *
- * Returns:
- * 0 on success, negative error code on failure.
- */
-ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
- const void *buffer, size_t size)
-{
- struct i2c_msg msg = {
- .addr = SCDC_I2C_SLAVE_ADDRESS,
- .flags = 0,
- .len = 1 + size,
- .buf = NULL,
- };
- void *data;
- int err;
-
- data = kmalloc(1 + size, GFP_KERNEL);
- if (!data)
- return -ENOMEM;
-
- msg.buf = data;
-
- memcpy(data, &offset, sizeof(offset));
- memcpy(data + 1, buffer, size);
-
- err = i2c_transfer(adapter, &msg, 1);
-
- kfree(data);
-
- if (err < 0)
- return err;
- if (err != 1)
- return -EPROTO;
-
- return 0;
-}
-EXPORT_SYMBOL(drm_scdc_write);
-
-/**
- * drm_scdc_get_scrambling_status - what is status of scrambling?
- * @adapter: I2C adapter for DDC channel
- *
- * Reads the scrambler status over SCDC, and checks the
- * scrambling status.
- *
- * Returns:
- * True if the scrambling is enabled, false otherwise.
- */
-bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter)
-{
- u8 status;
- int ret;
-
- ret = drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, &status);
- if (ret < 0) {
- DRM_DEBUG_KMS("Failed to read scrambling status: %d\n", ret);
- return false;
- }
-
- return status & SCDC_SCRAMBLING_STATUS;
-}
-EXPORT_SYMBOL(drm_scdc_get_scrambling_status);
-
-/**
- * drm_scdc_set_scrambling - enable scrambling
- * @adapter: I2C adapter for DDC channel
- * @enable: bool to indicate if scrambling is to be enabled/disabled
- *
- * Writes the TMDS config register over SCDC channel, and:
- * enables scrambling when enable = 1
- * disables scrambling when enable = 0
- *
- * Returns:
- * True if scrambling is set/reset successfully, false otherwise.
- */
-bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable)
-{
- u8 config;
- int ret;
-
- ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
- if (ret < 0) {
- DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret);
- return false;
- }
-
- if (enable)
- config |= SCDC_SCRAMBLING_ENABLE;
- else
- config &= ~SCDC_SCRAMBLING_ENABLE;
-
- ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
- if (ret < 0) {
- DRM_DEBUG_KMS("Failed to enable scrambling: %d\n", ret);
- return false;
- }
-
- return true;
-}
-EXPORT_SYMBOL(drm_scdc_set_scrambling);
-
-/**
- * drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
- * @adapter: I2C adapter for DDC channel
- * @set: ret or reset the high clock ratio
- *
- *
- * TMDS clock ratio calculations go like this:
- * TMDS character = 10 bit TMDS encoded value
- *
- * TMDS character rate = The rate at which TMDS characters are
- * transmitted (Mcsc)
- *
- * TMDS bit rate = 10x TMDS character rate
- *
- * As per the spec:
- * TMDS clock rate for pixel clock < 340 MHz = 1x the character
- * rate = 1/10 pixel clock rate
- *
- * TMDS clock rate for pixel clock > 340 MHz = 0.25x the character
- * rate = 1/40 pixel clock rate
- *
- * Writes to the TMDS config register over SCDC channel, and:
- * sets TMDS clock ratio to 1/40 when set = 1
- *
- * sets TMDS clock ratio to 1/10 when set = 0
- *
- * Returns:
- * True if write is successful, false otherwise.
- */
-bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set)
-{
- u8 config;
- int ret;
-
- ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
- if (ret < 0) {
- DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret);
- return false;
- }
-
- if (set)
- config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
- else
- config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
-
- ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
- if (ret < 0) {
- DRM_DEBUG_KMS("Failed to set TMDS clock ratio: %d\n", ret);
- return false;
- }
-
- /*
- * The spec says that a source should wait minimum 1ms and maximum
- * 100ms after writing the TMDS config for clock ratio. Lets allow a
- * wait of up to 2ms here.
- */
- usleep_range(1000, 2000);
- return true;
-}
-EXPORT_SYMBOL(drm_scdc_set_high_tmds_clock_ratio);
#include <linux/string_helpers.h>
+#include <drm/display/drm_scdc_helper.h>
#include <drm/drm_privacy_screen_consumer.h>
-#include <drm/drm_scdc_helper.h>
#include "i915_drv.h"
#include "intel_audio.h"
#include <drm/display/drm_hdcp_helper.h>
#include <drm/display/drm_hdmi_helper.h>
+#include <drm/display/drm_scdc_helper.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
-#include <drm/drm_scdc_helper.h>
#include <drm/intel_lpe_audio.h>
#include "i915_debugfs.h"
select IOMMU_API
select FW_LOADER
select DRM_DISPLAY_DP_HELPER
+ select DRM_DISPLAY_HDMI_HELPER
select DRM_DISPLAY_HELPER
select DRM_KMS_HELPER
select DRM_TTM
#include <linux/iopoll.h>
#include <drm/display/drm_dp_helper.h>
+#include <drm/display/drm_scdc_helper.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_edid.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_probe_helper.h>
-#include <drm/drm_scdc_helper.h>
#include <drm/drm_vblank.h>
#include <nvif/push507c.h>
depends on DRM
depends on OF
select DRM_DISPLAY_DP_HELPER
+ select DRM_DISPLAY_HDMI_HELPER
select DRM_DISPLAY_HELPER
select DRM_DP_AUX_BUS
select DRM_KMS_HELPER
#include <soc/tegra/pmc.h>
#include <drm/display/drm_dp_helper.h>
+#include <drm/display/drm_scdc_helper.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_debugfs.h>
#include <drm/drm_file.h>
#include <drm/drm_panel.h>
-#include <drm/drm_scdc_helper.h>
#include <drm/drm_simple_kms_helper.h>
#include "dc.h"
*/
#include <drm/display/drm_hdmi_helper.h>
+#include <drm/display/drm_scdc_helper.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_simple_kms_helper.h>
-#include <drm/drm_scdc_helper.h>
#include <linux/clk.h>
#include <linux/component.h>
#include <linux/i2c.h>
--- /dev/null
+/*
+ * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef DRM_SCDC_H
+#define DRM_SCDC_H
+
+#define SCDC_SINK_VERSION 0x01
+
+#define SCDC_SOURCE_VERSION 0x02
+
+#define SCDC_UPDATE_0 0x10
+#define SCDC_READ_REQUEST_TEST (1 << 2)
+#define SCDC_CED_UPDATE (1 << 1)
+#define SCDC_STATUS_UPDATE (1 << 0)
+
+#define SCDC_UPDATE_1 0x11
+
+#define SCDC_TMDS_CONFIG 0x20
+#define SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 (1 << 1)
+#define SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1)
+#define SCDC_SCRAMBLING_ENABLE (1 << 0)
+
+#define SCDC_SCRAMBLER_STATUS 0x21
+#define SCDC_SCRAMBLING_STATUS (1 << 0)
+
+#define SCDC_CONFIG_0 0x30
+#define SCDC_READ_REQUEST_ENABLE (1 << 0)
+
+#define SCDC_STATUS_FLAGS_0 0x40
+#define SCDC_CH2_LOCK (1 << 3)
+#define SCDC_CH1_LOCK (1 << 2)
+#define SCDC_CH0_LOCK (1 << 1)
+#define SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK)
+#define SCDC_CLOCK_DETECT (1 << 0)
+
+#define SCDC_STATUS_FLAGS_1 0x41
+
+#define SCDC_ERR_DET_0_L 0x50
+#define SCDC_ERR_DET_0_H 0x51
+#define SCDC_ERR_DET_1_L 0x52
+#define SCDC_ERR_DET_1_H 0x53
+#define SCDC_ERR_DET_2_L 0x54
+#define SCDC_ERR_DET_2_H 0x55
+#define SCDC_CHANNEL_VALID (1 << 7)
+
+#define SCDC_ERR_DET_CHECKSUM 0x56
+
+#define SCDC_TEST_CONFIG_0 0xc0
+#define SCDC_TEST_READ_REQUEST (1 << 7)
+#define SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f)
+
+#define SCDC_MANUFACTURER_IEEE_OUI 0xd0
+#define SCDC_MANUFACTURER_IEEE_OUI_SIZE 3
+
+#define SCDC_DEVICE_ID 0xd3
+#define SCDC_DEVICE_ID_SIZE 8
+
+#define SCDC_DEVICE_HARDWARE_REVISION 0xdb
+#define SCDC_GET_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
+#define SCDC_GET_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf)
+
+#define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc
+#define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd
+
+#define SCDC_MANUFACTURER_SPECIFIC 0xde
+#define SCDC_MANUFACTURER_SPECIFIC_SIZE 34
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef DRM_SCDC_HELPER_H
+#define DRM_SCDC_HELPER_H
+
+#include <linux/types.h>
+
+#include <drm/display/drm_scdc.h>
+
+struct i2c_adapter;
+
+ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,
+ size_t size);
+ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
+ const void *buffer, size_t size);
+
+/**
+ * drm_scdc_readb - read a single byte from SCDC
+ * @adapter: I2C adapter
+ * @offset: offset of register to read
+ * @value: return location for the register value
+ *
+ * Reads a single byte from SCDC. This is a convenience wrapper around the
+ * drm_scdc_read() function.
+ *
+ * Returns:
+ * 0 on success or a negative error code on failure.
+ */
+static inline int drm_scdc_readb(struct i2c_adapter *adapter, u8 offset,
+ u8 *value)
+{
+ return drm_scdc_read(adapter, offset, value, sizeof(*value));
+}
+
+/**
+ * drm_scdc_writeb - write a single byte to SCDC
+ * @adapter: I2C adapter
+ * @offset: offset of register to read
+ * @value: return location for the register value
+ *
+ * Writes a single byte to SCDC. This is a convenience wrapper around the
+ * drm_scdc_write() function.
+ *
+ * Returns:
+ * 0 on success or a negative error code on failure.
+ */
+static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset,
+ u8 value)
+{
+ return drm_scdc_write(adapter, offset, &value, sizeof(value));
+}
+
+bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter);
+
+bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable);
+bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set);
+
+#endif
+++ /dev/null
-/*
- * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sub license,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef DRM_SCDC_HELPER_H
-#define DRM_SCDC_HELPER_H
-
-#include <linux/i2c.h>
-#include <linux/types.h>
-
-#define SCDC_SINK_VERSION 0x01
-
-#define SCDC_SOURCE_VERSION 0x02
-
-#define SCDC_UPDATE_0 0x10
-#define SCDC_READ_REQUEST_TEST (1 << 2)
-#define SCDC_CED_UPDATE (1 << 1)
-#define SCDC_STATUS_UPDATE (1 << 0)
-
-#define SCDC_UPDATE_1 0x11
-
-#define SCDC_TMDS_CONFIG 0x20
-#define SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 (1 << 1)
-#define SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1)
-#define SCDC_SCRAMBLING_ENABLE (1 << 0)
-
-#define SCDC_SCRAMBLER_STATUS 0x21
-#define SCDC_SCRAMBLING_STATUS (1 << 0)
-
-#define SCDC_CONFIG_0 0x30
-#define SCDC_READ_REQUEST_ENABLE (1 << 0)
-
-#define SCDC_STATUS_FLAGS_0 0x40
-#define SCDC_CH2_LOCK (1 << 3)
-#define SCDC_CH1_LOCK (1 << 2)
-#define SCDC_CH0_LOCK (1 << 1)
-#define SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK)
-#define SCDC_CLOCK_DETECT (1 << 0)
-
-#define SCDC_STATUS_FLAGS_1 0x41
-
-#define SCDC_ERR_DET_0_L 0x50
-#define SCDC_ERR_DET_0_H 0x51
-#define SCDC_ERR_DET_1_L 0x52
-#define SCDC_ERR_DET_1_H 0x53
-#define SCDC_ERR_DET_2_L 0x54
-#define SCDC_ERR_DET_2_H 0x55
-#define SCDC_CHANNEL_VALID (1 << 7)
-
-#define SCDC_ERR_DET_CHECKSUM 0x56
-
-#define SCDC_TEST_CONFIG_0 0xc0
-#define SCDC_TEST_READ_REQUEST (1 << 7)
-#define SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f)
-
-#define SCDC_MANUFACTURER_IEEE_OUI 0xd0
-#define SCDC_MANUFACTURER_IEEE_OUI_SIZE 3
-
-#define SCDC_DEVICE_ID 0xd3
-#define SCDC_DEVICE_ID_SIZE 8
-
-#define SCDC_DEVICE_HARDWARE_REVISION 0xdb
-#define SCDC_GET_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
-#define SCDC_GET_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf)
-
-#define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc
-#define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd
-
-#define SCDC_MANUFACTURER_SPECIFIC 0xde
-#define SCDC_MANUFACTURER_SPECIFIC_SIZE 34
-
-ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,
- size_t size);
-ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
- const void *buffer, size_t size);
-
-/**
- * drm_scdc_readb - read a single byte from SCDC
- * @adapter: I2C adapter
- * @offset: offset of register to read
- * @value: return location for the register value
- *
- * Reads a single byte from SCDC. This is a convenience wrapper around the
- * drm_scdc_read() function.
- *
- * Returns:
- * 0 on success or a negative error code on failure.
- */
-static inline int drm_scdc_readb(struct i2c_adapter *adapter, u8 offset,
- u8 *value)
-{
- return drm_scdc_read(adapter, offset, value, sizeof(*value));
-}
-
-/**
- * drm_scdc_writeb - write a single byte to SCDC
- * @adapter: I2C adapter
- * @offset: offset of register to read
- * @value: return location for the register value
- *
- * Writes a single byte to SCDC. This is a convenience wrapper around the
- * drm_scdc_write() function.
- *
- * Returns:
- * 0 on success or a negative error code on failure.
- */
-static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset,
- u8 value)
-{
- return drm_scdc_write(adapter, offset, &value, sizeof(value));
-}
-
-bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter);
-
-bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable);
-bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set);
-#endif
projects / kernel.git / commitdiff