drm/i915/execlists: Reduce barrier on context switch to a wmb()

Having been forced to reduce Braswell back to using the aliasing ppgtt,
the coherency issue we previously observed cannot impact us. Reduce the
performance penalty imposed on all platforms from using the mfence to a
mere sfence.

References: cf66b8a0ba14 ("drm/i915/execlists: Apply a full mb before execution for Braswell")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191110185806.17413-10-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 1975fe4775d245aaaa93937bf820a0b4c0088e80..e57345795c083e167ff2729d970dee5a9a25a032 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1218,13 +1218,8 @@ static u64 execlists_update_context(const struct i915_request *rq)
         * may not be visible to the HW prior to the completion of the UC
         * register write and that we may begin execution from the context
         * before its image is complete leading to invalid PD chasing.
-        *
-        * Furthermore, Braswell, at least, wants a full mb to be sure that
-        * the writes are coherent in memory (visible to the GPU) prior to
-        * execution, and not just visible to other CPUs (as is the result of
-        * wmb).
         */
-       mb();
+       wmb();
 
        desc = ce->lrc_desc;
        ce->lrc_desc &= ~CTX_DESC_FORCE_RESTORE;