drm/msm/dpu: update UBWC config for sm8150 and sm8250

Update the UBWC registers to the right values for sm8150 and sm8250.

This removes broken dpu_hw_reset_ubwc, which doesn't work because the
"force blk offset to zero to access beginning of register region" hack is
copied from downstream, where mapped region starts 0x1000 below what is
used in the upstream driver.

Also simplifies the overly complicated change that was introduced in
399807e090bff2d4cf03 to work around dpu_hw_reset_ubwc being broken.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d7b2b0daed6884f01ad9127a269d2740457ca086..a97f6d2e5a089c925ce7abb6362c77effb02051d 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1088,7 +1088,6 @@ static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
 {
        struct dpu_encoder_virt *dpu_enc = NULL;
        struct msm_drm_private *priv;
-       struct dpu_kms *dpu_kms;
        int i;
 
        if (!drm_enc || !drm_enc->dev) {
@@ -1097,7 +1096,6 @@ static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
        }
 
        priv = drm_enc->dev->dev_private;
-       dpu_kms = to_dpu_kms(priv->kms);
 
        dpu_enc = to_dpu_encoder_virt(drm_enc);
        if (!dpu_enc || !dpu_enc->cur_master) {
@@ -1105,12 +1103,6 @@ static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
                return;
        }
 
-       if (dpu_enc->cur_master->hw_mdptop &&
-                       dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc)
-               dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc(
-                               dpu_enc->cur_master->hw_mdptop,
-                               dpu_kms->catalog);
-
        _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
 
        if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI &&

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index f7de43838c69cbad996b509784fd512b409f0d15..63512753b369e58f96ddeca236f901f2ac0a4be1 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -37,7 +37,9 @@
 #define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */
 #define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */
 #define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */
-#define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sdm855 v1.0 */
+#define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */
+#define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */
+#define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
 #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
 
 
@@ -65,10 +67,9 @@ enum {
        DPU_HW_UBWC_VER_10 = 0x100,
        DPU_HW_UBWC_VER_20 = 0x200,
        DPU_HW_UBWC_VER_30 = 0x300,
+       DPU_HW_UBWC_VER_40 = 0x400,
 };
 
-#define IS_UBWC_20_SUPPORTED(rev)       ((rev) >= DPU_HW_UBWC_VER_20)
-
 /**
  * MDP TOP BLOCK features
  * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe
@@ -447,7 +448,6 @@ struct dpu_clk_ctrl_reg {
 struct dpu_mdp_cfg {
        DPU_HW_BLK_INFO;
        u32 highest_bank_bit;
-       u32 ubwc_static;
        u32 ubwc_swizzle;
        struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
 };

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 82c5dbfdabc7594ac0eaf9cbe43ef438715387d8..c940b69435e162d1a10d2854a497331067f9d584 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -303,11 +303,25 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
                DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
                        DPU_FETCH_CONFIG_RESET_VALUE |
                        ctx->mdp->highest_bank_bit << 18);
-               if (IS_UBWC_20_SUPPORTED(ctx->catalog->caps->ubwc_version)) {
+               switch (ctx->catalog->caps->ubwc_version) {
+               case DPU_HW_UBWC_VER_10:
+                       /* TODO: UBWC v1 case */
+                       break;
+               case DPU_HW_UBWC_VER_20:
                        fast_clear = fmt->alpha_enable ? BIT(31) : 0;
                        DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
                                        fast_clear | (ctx->mdp->ubwc_swizzle) |
                                        (ctx->mdp->highest_bank_bit << 4));
+                       break;
+               case DPU_HW_UBWC_VER_30:
+                       DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+                                       BIT(30) | (ctx->mdp->ubwc_swizzle) |
+                                       (ctx->mdp->highest_bank_bit << 4));
+                       break;
+               case DPU_HW_UBWC_VER_40:
+                       DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+                                       DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
+                       break;
                }
        }
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index f9af52ae9f3e1d09ff973d5febee43e626843a06..01b76766a9a811dfc4e5ca32ac267ec7fe8db08d 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -8,7 +8,6 @@
 #include "dpu_kms.h"
 
 #define SSPP_SPARE                        0x28
-#define UBWC_STATIC                       0x144
 
 #define FLD_SPLIT_DISPLAY_CMD             BIT(1)
 #define FLD_SMART_PANEL_FREE_RUN          BIT(2)
@@ -249,22 +248,6 @@ static void dpu_hw_get_safe_status(struct dpu_hw_mdp *mdp,
        status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1;
 }
 
-static void dpu_hw_reset_ubwc(struct dpu_hw_mdp *mdp, struct dpu_mdss_cfg *m)
-{
-       struct dpu_hw_blk_reg_map c;
-
-       if (!mdp || !m)
-               return;
-
-       if (!IS_UBWC_20_SUPPORTED(m->caps->ubwc_version))
-               return;
-
-       /* force blk offset to zero to access beginning of register region */
-       c = mdp->hw;
-       c.blk_off = 0x0;
-       DPU_REG_WRITE(&c, UBWC_STATIC, m->mdp[0].ubwc_static);
-}
-
 static void dpu_hw_intf_audio_select(struct dpu_hw_mdp *mdp)
 {
        struct dpu_hw_blk_reg_map *c;
@@ -285,7 +268,6 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
        ops->get_danger_status = dpu_hw_get_danger_status;
        ops->setup_vsync_source = dpu_hw_setup_vsync_source;
        ops->get_safe_status = dpu_hw_get_safe_status;
-       ops->reset_ubwc = dpu_hw_reset_ubwc;
        ops->intf_audio_select = dpu_hw_intf_audio_select;
 }
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
index 1d9d32edf619d4ae790b338a72d721f7313ec1cd..8018fff5667aa4f487df9ef5d155dcbbbaf8afd6 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
@@ -126,13 +126,6 @@ struct dpu_hw_mdp_ops {
        void (*get_safe_status)(struct dpu_hw_mdp *mdp,
                        struct dpu_danger_safe_status *status);
 
-       /**
-        * reset_ubwc - reset top level UBWC configuration
-        * @mdp: mdp top context driver
-        * @m: pointer to mdss catalog data
-        */
-       void (*reset_ubwc)(struct dpu_hw_mdp *mdp, struct dpu_mdss_cfg *m);
-
        /**
         * intf_audio_select - select the external interface for audio
         * @mdp: mdp top context driver

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index 9f20b84d5c0a1c34a2f4bd07b7de5efa1d9d41b1..7d3fdbb00e7eb3eecfb5ea5c33166f7b2cd97842 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
@@ -15,6 +15,10 @@
 #define HW_REV                         0x0
 #define HW_INTR_STATUS                 0x0010
 
+#define UBWC_STATIC                    0x144
+#define UBWC_CTRL_2                    0x150
+#define UBWC_PREDICTION_MODE           0x154
+
 /* Max BW defined in KBps */
 #define MAX_BW                         6800000
 
@@ -23,17 +27,6 @@ struct dpu_irq_controller {
        struct irq_domain *domain;
 };
 
-struct dpu_hw_cfg {
-       u32 val;
-       u32 offset;
-};
-
-struct dpu_mdss_hw_init_handler {
-       u32 hw_rev;
-       u32 hw_reg_count;
-       struct dpu_hw_cfg* hw_cfg;
-};
-
 struct dpu_mdss {
        struct msm_mdss base;
        void __iomem *mmio;
@@ -43,44 +36,6 @@ struct dpu_mdss {
        u32 num_paths;
 };
 
-static struct dpu_hw_cfg hw_cfg[] = {
-    {
-       /* UBWC global settings */
-       .val = 0x1E,
-       .offset = 0x144,
-    }
-};
-
-static struct dpu_mdss_hw_init_handler cfg_handler[] = {
-    { .hw_rev = DPU_HW_VER_620,
-      .hw_reg_count = ARRAY_SIZE(hw_cfg),
-      .hw_cfg = hw_cfg
-    },
-};
-
-static void dpu_mdss_hw_init(struct dpu_mdss *dpu_mdss, u32 hw_rev)
-{
-       int i;
-       u32 count = 0;
-       struct dpu_hw_cfg *hw_cfg = NULL;
-
-       for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) {
-               if (cfg_handler[i].hw_rev == hw_rev) {
-                       hw_cfg = cfg_handler[i].hw_cfg;
-                       count = cfg_handler[i].hw_reg_count;
-                       break;
-           }
-       }
-
-       for (i = 0; i < count; i++ ) {
-               writel_relaxed(hw_cfg->val,
-                       dpu_mdss->mmio + hw_cfg->offset);
-               hw_cfg++;
-       }
-
-    return;
-}
-
 static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev,
                                                struct dpu_mdss *dpu_mdss)
 {
@@ -223,7 +178,6 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
        struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
        struct dss_module_power *mp = &dpu_mdss->mp;
        int ret;
-       u32 mdss_rev;
 
        dpu_mdss_icc_request_bw(mdss);
 
@@ -233,8 +187,25 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
                return ret;
        }
 
-       mdss_rev = readl_relaxed(dpu_mdss->mmio + HW_REV);
-       dpu_mdss_hw_init(dpu_mdss, mdss_rev);
+       /*
+        * ubwc config is part of the "mdss" region which is not accessible
+        * from the rest of the driver. hardcode known configurations here
+        */
+       switch (readl_relaxed(dpu_mdss->mmio + HW_REV)) {
+       case DPU_HW_VER_500:
+       case DPU_HW_VER_501:
+               writel_relaxed(0x420, dpu_mdss->mmio + UBWC_STATIC);
+               break;
+       case DPU_HW_VER_600:
+               /* TODO: 0x102e for LP_DDR4 */
+               writel_relaxed(0x103e, dpu_mdss->mmio + UBWC_STATIC);
+               writel_relaxed(2, dpu_mdss->mmio + UBWC_CTRL_2);
+               writel_relaxed(1, dpu_mdss->mmio + UBWC_PREDICTION_MODE);
+               break;
+       case DPU_HW_VER_620:
+               writel_relaxed(0x1e, dpu_mdss->mmio + UBWC_STATIC);
+               break;
+       }
 
        return ret;
 }