drm/i915: Nuke pointless div by 64bit

Bunch of places use a 64bit divisor needlessly. Switch
to 32bit divisor.

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200302143943.32676-1-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index c533f569dd42cf83c02745833954ee24ec26ce75..2e611551d809e5a60726ba6f6a8185dc35bc2d93 100644 (file)
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1612,10 +1612,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
        struct drm_i915_gem_object *bo;
        struct i915_vma *vma;
        const u64 delay_ticks = 0xffffffffffffffff -
-               DIV64_U64_ROUND_UP(
-                       atomic64_read(&stream->perf->noa_programming_delay) *
-                       RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
-                       1000000ull);
+               DIV_ROUND_UP_ULL(atomic64_read(&stream->perf->noa_programming_delay) *
+                                RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
+                                1000000);
        const u32 base = stream->engine->mmio_base;
 #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
        u32 *batch, *ts0, *cs, *jump;
@@ -3485,8 +3484,8 @@ err:
 
 static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
 {
-       return div64_u64(1000000000ULL * (2ULL << exponent),
-                        1000ULL * RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_khz);
+       return div_u64(1000000 * (2ULL << exponent),
+                      RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_khz);
 }
 
 /**