ARM: dts: r9a06g032: describe MII converter

Add the MII converter node which describes the MII converter that is
present on the RZ/N1 SoC.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index d3665910958bbf6d9d0a90b323ab6b4aa433ebfc..f6241af3311225cbc2ad5d5eb8f4d0919723b589 100644 (file)
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -304,6 +304,45 @@
                        data-width = <8>;
                };
 
+               eth_miic: eth-miic@44030000 {
+                       compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x44030000 0x10000>;
+                       clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
+                                <&sysctrl R9A06G032_CLK_RGMII_REF>,
+                                <&sysctrl R9A06G032_CLK_RMII_REF>,
+                                <&sysctrl R9A06G032_HCLK_SWITCH_RG>;
+                       clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
+                       power-domains = <&sysctrl>;
+                       status = "disabled";
+
+                       mii_conv1: mii-conv@1 {
+                               reg = <1>;
+                               status = "disabled";
+                       };
+
+                       mii_conv2: mii-conv@2 {
+                               reg = <2>;
+                               status = "disabled";
+                       };
+
+                       mii_conv3: mii-conv@3 {
+                               reg = <3>;
+                               status = "disabled";
+                       };
+
+                       mii_conv4: mii-conv@4 {
+                               reg = <4>;
+                               status = "disabled";
+                       };
+
+                       mii_conv5: mii-conv@5 {
+                               reg = <5>;
+                               status = "disabled";
+                       };
+               };
+
                gic: interrupt-controller@44101000 {
                        compatible = "arm,gic-400", "arm,cortex-a7-gic";
                        interrupt-controller;