drm/i915: Extract tile_row_size for fencing

Computing the tile row size of a tiled object (for use with fence
registers) is repeated, so extract it to a common helper.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/20170109161613.11881-1-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ed3cd1a5f9bbf99e58c375d63c5db4d49ff76dfb..e8e278f6312e417579728c1f373ddfa9e66e5fb0 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1696,12 +1696,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 
 static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
 {
-       u64 size;
-
-       size = i915_gem_object_get_stride(obj);
-       size *= i915_gem_object_get_tiling(obj) == I915_TILING_Y ? 32 : 8;
-
-       return size >> PAGE_SHIFT;
+       return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT;
 }
 
 /**

diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index 775059e19ab9d2b72fa42f09f3741f9a91cb7aad..399ae7f73184d5971addc30af220ff83d34780b1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -77,16 +77,14 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
 
        val = 0;
        if (vma) {
-               unsigned int tiling = i915_gem_object_get_tiling(vma->obj);
-               bool is_y_tiled = tiling == I915_TILING_Y;
                unsigned int stride = i915_gem_object_get_stride(vma->obj);
-               u32 row_size = stride * (is_y_tiled ? 32 : 8);
+               u32 row_size = i915_gem_object_get_tile_row_size(vma->obj);
                u32 size = rounddown((u32)vma->node.size, row_size);
 
                val = ((vma->node.start + size - 4096) & 0xfffff000) << 32;
                val |= vma->node.start & 0xfffff000;
                val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
-               if (is_y_tiled)
+               if (i915_gem_object_get_tiling(vma->obj) == I915_TILING_Y)
                        val |= BIT(I965_FENCE_TILING_Y_SHIFT);
                val |= I965_FENCE_REG_VALID;
        }

diff --git a/drivers/gpu/drm/i915/i915_gem_object.h b/drivers/gpu/drm/i915/i915_gem_object.h
index 6a368de9d81e7be2d6e775b3cca7c7187e6a4c88..ed3f4d5fd49f40bba5c2f87453ecf28dd013c1af 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -317,6 +317,26 @@ i915_gem_object_get_stride(struct drm_i915_gem_object *obj)
        return obj->tiling_and_stride & STRIDE_MASK;
 }
 
+static inline unsigned int
+i915_gem_tile_height(unsigned int tiling)
+{
+       GEM_BUG_ON(!tiling);
+       return tiling == I915_TILING_Y ? 32 : 8;
+}
+
+static inline unsigned int
+i915_gem_object_get_tile_height(struct drm_i915_gem_object *obj)
+{
+       return i915_gem_tile_height(i915_gem_object_get_tiling(obj));
+}
+
+static inline unsigned int
+i915_gem_object_get_tile_row_size(struct drm_i915_gem_object *obj)
+{
+       return (i915_gem_object_get_stride(obj) *
+               i915_gem_object_get_tile_height(obj));
+}
+
 static inline struct intel_engine_cs *
 i915_gem_object_last_write_engine(struct drm_i915_gem_object *obj)
 {