powerpc/32s: Rename PTE_SIZE to PTE_T_SIZE

PTE_SIZE means PTE page table size in most placed, whereas
in hash_low.S in means size of one entry in the table.

Rename it PTE_T_SIZE, and define it directly in hash_low.S
instead of going through asm-offsets.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/83a008a9fd6cc3f2bbcb470f592555d260ed7a3d.1623063174.git.christophe.leroy@csgroup.eu

diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index c46685c9b2c644cd92baaddec0f4439450ed2b59..8599cf4f799c74c2ad76678eefe8e47f206da9e5 100644 (file)
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -354,8 +354,6 @@ int main(void)
        DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
 #endif
 
-       DEFINE(PTE_SIZE, sizeof(pte_t));
-
 #ifdef CONFIG_KVM
        OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack);
        OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid);

diff --git a/arch/powerpc/mm/book3s32/hash_low.S b/arch/powerpc/mm/book3s32/hash_low.S
index fb4233a5bdf7d791650cb79a15ca99e2e557ba2b..6925ce9985571e2fb9d138fe5a2e86ea48f26f07 100644 (file)
--- a/arch/powerpc/mm/book3s32/hash_low.S
+++ b/arch/powerpc/mm/book3s32/hash_low.S
@@ -27,8 +27,10 @@
 #include <asm/code-patching-asm.h>
 
 #ifdef CONFIG_PTE_64BIT
+#define PTE_T_SIZE             8
 #define PTE_FLAGS_OFFSET       4       /* offset of PTE flags, in bytes */
 #else
+#define PTE_T_SIZE             4
 #define PTE_FLAGS_OFFSET       0
 #endif
 
@@ -488,7 +490,7 @@ _GLOBAL(flush_hash_pages)
        bne     2f
        ble     cr1,19f
        addi    r4,r4,0x1000
-       addi    r5,r5,PTE_SIZE
+       addi    r5,r5,PTE_T_SIZE
        addi    r6,r6,-1
        b       1b
 
@@ -573,7 +575,7 @@ _GLOBAL(flush_hash_pages)
 
 8:     ble     cr1,9f                  /* if all ptes checked */
 81:    addi    r6,r6,-1
-       addi    r5,r5,PTE_SIZE
+       addi    r5,r5,PTE_T_SIZE
        addi    r4,r4,0x1000
        lwz     r0,0(r5)                /* check next pte */
        cmpwi   cr1,r6,1