]> git.baikalelectronics.ru Git - uboot.git/commitdiff
stm32mp1: update print_cpuinfo()
authorPatrick Delaunay <patrick.delaunay@st.com>
Wed, 27 Feb 2019 16:01:13 +0000 (17:01 +0100)
committerPatrick Delaunay <patrick.delaunay@st.com>
Fri, 12 Apr 2019 14:09:13 +0000 (16:09 +0200)
Display CPU part number and package information.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
arch/arm/mach-stm32mp/cpu.c
arch/arm/mach-stm32mp/include/mach/sys_proto.h

index 753ff3e4dbd1ccf48eb58d5c1c2b8830ad398144..206b82e9e929d3e129713160113cc7774ea97698 100644 (file)
 #define BOOTROM_INSTANCE_SHIFT 16
 
 /* BSEC OTP index */
+#define BSEC_OTP_RPN   1
 #define BSEC_OTP_SERIAL        13
+#define BSEC_OTP_PKG   16
 #define BSEC_OTP_MAC   57
 
+/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
+#define RPN_SHIFT      0
+#define RPN_MASK       GENMASK(7, 0)
+
+/* Package = bit 27:29 of OTP16
+ * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
+ * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
+ * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
+ * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
+ * - others: Reserved
+ */
+#define PKG_SHIFT      27
+#define PKG_MASK       GENMASK(2, 0)
+
+#define PKG_AA_LBGA448 4
+#define PKG_AB_LBGA354 3
+#define PKG_AC_TFBGA361        2
+#define PKG_AD_TFBGA257        1
+
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 #ifndef CONFIG_STM32MP1_TRUSTED
 static void security_init(void)
@@ -215,25 +236,94 @@ u32 get_cpu_rev(void)
        return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
 }
 
+static u32 get_otp(int index, int shift, int mask)
+{
+       int ret;
+       struct udevice *dev;
+       u32 otp = 0;
+
+       ret = uclass_get_device_by_driver(UCLASS_MISC,
+                                         DM_GET_DRIVER(stm32mp_bsec),
+                                         &dev);
+
+       if (!ret)
+               ret = misc_read(dev, STM32_BSEC_SHADOW(index),
+                               &otp, sizeof(otp));
+
+       return (otp >> shift) & mask;
+}
+
+/* Get Device Part Number (RPN) from OTP */
+static u32 get_cpu_rpn(void)
+{
+       return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
+}
+
 u32 get_cpu_type(void)
 {
-       return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
+       u32 id;
+
+       id = (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
+
+       return (id << 16) | get_cpu_rpn();
+}
+
+/* Get Package options from OTP */
+static u32 get_cpu_package(void)
+{
+       return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
 }
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
-       char *cpu_s, *cpu_r;
+       char *cpu_s, *cpu_r, *pkg;
 
+       /* MPUs Part Numbers */
        switch (get_cpu_type()) {
-       case CPU_STMP32MP15x:
-               cpu_s = "15x";
+       case CPU_STM32MP157Cxx:
+               cpu_s = "157C";
+               break;
+       case CPU_STM32MP157Axx:
+               cpu_s = "157A";
+               break;
+       case CPU_STM32MP153Cxx:
+               cpu_s = "153C";
+               break;
+       case CPU_STM32MP153Axx:
+               cpu_s = "153A";
+               break;
+       case CPU_STM32MP151Cxx:
+               cpu_s = "151C";
+               break;
+       case CPU_STM32MP151Axx:
+               cpu_s = "151A";
+               break;
+       default:
+               cpu_s = "????";
+               break;
+       }
+
+       /* Package */
+       switch (get_cpu_package()) {
+       case PKG_AA_LBGA448:
+               pkg = "AA";
+               break;
+       case PKG_AB_LBGA354:
+               pkg = "AB";
+               break;
+       case PKG_AC_TFBGA361:
+               pkg = "AC";
+               break;
+       case PKG_AD_TFBGA257:
+               pkg = "AD";
                break;
        default:
-               cpu_s = "?";
+               pkg = "??";
                break;
        }
 
+       /* REVISION */
        switch (get_cpu_rev()) {
        case CPU_REVA:
                cpu_r = "A";
@@ -246,7 +336,7 @@ int print_cpuinfo(void)
                break;
        }
 
-       printf("CPU: STM32MP%s.%s\n", cpu_s, cpu_r);
+       printf("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r);
 
        return 0;
 }
index 8b426c08f691730ca1afd67ebbd86b4dbdbf4c50..71a3ba794d11b8f90b61bf5bb23ea3229798dfbe 100644 (file)
@@ -3,9 +3,15 @@
  * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved
  */
 
-#define CPU_STMP32MP15x        0x500
+/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0)*/
+#define CPU_STM32MP157Cxx      0x05000000
+#define CPU_STM32MP157Axx      0x05000001
+#define CPU_STM32MP153Cxx      0x05000024
+#define CPU_STM32MP153Axx      0x05000025
+#define CPU_STM32MP151Cxx      0x0500002E
+#define CPU_STM32MP151Axx      0x0500002F
 
-/* return CPU_STMP32MPxx constants */
+/* return CPU_STMP32MP...Xxx constants */
 u32 get_cpu_type(void);
 
 #define CPU_REVA       0x1000