feat(cpus): add support for blackhawk cpu

Add basic CPU library code to support the Blackhawk CPU,
BlackHawk core is based out of Hunter ELP core,
so overall library code was adapted based on that.

Change-Id: I4750e774732218ee669dceb734cd107f46b78492
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

diff --git a/include/lib/cpus/aarch64/cortex_blackhawk.h b/include/lib/cpus/aarch64/cortex_blackhawk.h
new file mode 100644 (file)
index 0000000..bfb3039
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_blackhawk.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_BLACKHAWK_H
+#define CORTEX_BLACKHAWK_H
+
+#define CORTEX_BLACKHAWK_MIDR                                  U(0x410FD850)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_BLACKHAWK_CPUECTLR_EL1                          S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_BLACKHAWK_CPUPWRCTLR_EL1                                S3_0_C15_C2_7
+#define CORTEX_BLACKHAWK_CPUPWRCTLR_EL1_CORE_PWRDN_BIT         U(1)
+
+#endif /* CORTEX_BLACKHAWK_H */

diff --git a/lib/cpus/aarch64/cortex_blackhawk.S b/lib/cpus/aarch64/cortex_blackhawk.S
new file mode 100644 (file)
index 0000000..8dac4e9
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_blackhawk.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_blackhawk.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex blackhawk must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex blackhawk supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+func cortex_blackhawk_reset_func
+       /* Disable speculative loads */
+       msr     SSBS, xzr
+       isb
+       ret
+endfunc cortex_blackhawk_reset_func
+
+       /* ----------------------------------------------------
+        * HW will do the cache maintenance while powering down
+        * ----------------------------------------------------
+        */
+func cortex_blackhawk_core_pwr_dwn
+       /* ---------------------------------------------------
+        * Enable CPU power down bit in power control register
+        * ---------------------------------------------------
+        */
+       mrs     x0, CORTEX_BLACKHAWK_CPUPWRCTLR_EL1
+       orr     x0, x0, #CORTEX_BLACKHAWK_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+       msr     CORTEX_BLACKHAWK_CPUPWRCTLR_EL1, x0
+       isb
+       ret
+endfunc cortex_blackhawk_core_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex Blackhawk. Must follow AAPCS.
+ */
+func cortex_blackhawk_errata_report
+       ret
+endfunc cortex_blackhawk_errata_report
+#endif
+
+       /* ---------------------------------------------
+        * This function provides Cortex Blackhawk specific
+        * register information for crash reporting.
+        * It needs to return with x6 pointing to
+        * a list of register names in ascii and
+        * x8 - x15 having values of registers to be
+        * reported.
+        * ---------------------------------------------
+        */
+.section .rodata.cortex_blackhawk_regs, "aS"
+cortex_blackhawk_regs:  /* The ascii list of register names to be reported */
+       .asciz  "cpuectlr_el1", ""
+
+func cortex_blackhawk_cpu_reg_dump
+       adr     x6, cortex_blackhawk_regs
+       mrs     x8, CORTEX_BLACKHAWK_CPUECTLR_EL1
+       ret
+endfunc cortex_blackhawk_cpu_reg_dump
+
+declare_cpu_ops cortex_blackhawk, CORTEX_BLACKHAWK_MIDR, \
+       cortex_blackhawk_reset_func, \
+       cortex_blackhawk_core_pwr_dwn

diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 728225ae3e2262f24535a3b550d062610159de40..e6a207c5ccc9298ce4ece072bd1475483dd4f291 100644 (file)
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -199,7 +199,8 @@ else
                                        lib/cpus/aarch64/cortex_hunter_elp_arm.S \
                                        lib/cpus/aarch64/cortex_x2.S            \
                                        lib/cpus/aarch64/neoverse_poseidon.S    \
-                                       lib/cpus/aarch64/cortex_chaberton.S
+                                       lib/cpus/aarch64/cortex_chaberton.S     \
+                                       lib/cpus/aarch64/cortex_blackhawk.S
        endif
        # AArch64/AArch32 cores
        FVP_CPU_LIBS    +=      lib/cpus/aarch64/cortex_a55.S           \