drm/meson: venc: add support for YUV420 setup

This patch adds encoding support for the YUV420 output from the
Amlogic Meson SoCs Video Processing Unit to the HDMI Controller.

The YUV420 is obtained by generating a YUV444 pixel stream like
the classic HDMI display modes, but then the Video Encoder output
can be configured to down-sample the YUV444 pixel stream to a YUV420
stream.

In addition if pixel stream down-sampling, the Y Cb Cr components must
also be mapped differently to align with the HDMI2.0 specifications.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jernej Škrabec <jernej.skrabec@siol.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20200304104052.17196-10-narmstrong@baylibre.com

diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
index 72c118142eaf45970063bbf80a49312530a87993..b2105c0fe205ce8299fe3f970041516888dd5bc4 100644 (file)
--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
@@ -752,7 +752,8 @@ static void meson_venc_hdmi_encoder_mode_set(struct drm_bridge *bridge,
        DRM_DEBUG_DRIVER("\"%s\" vic %d\n", mode->name, vic);
 
        /* VENC + VENC-DVI Mode setup */
-       meson_venc_hdmi_mode_set(priv, vic, mode);
+       meson_venc_hdmi_mode_set(priv, vic, ycrcb_map, false,
+                                VPU_HDMI_OUTPUT_CBYCR);
 
        /* VCLK Set clock */
        dw_hdmi_set_vclk(dw_hdmi, mode);

diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
index a9ab78970bfe551f38a9c74922f9ac677837500f..f93c725b6f02d1abafa29db0c81d266126bd01bd 100644 (file)
--- a/drivers/gpu/drm/meson/meson_venc.c
+++ b/drivers/gpu/drm/meson/meson_venc.c
@@ -946,6 +946,8 @@ bool meson_venc_hdmi_venc_repeat(int vic)
 EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat);
 
 void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
+                             unsigned int ycrcb_map,
+                             bool yuv420_mode,
                              const struct drm_display_mode *mode)
 {
        union meson_hdmi_venc_mode *vmode = NULL;
@@ -1528,14 +1530,14 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
        if (mode->flags & DRM_MODE_FLAG_PVSYNC)
                reg |= VPU_HDMI_INV_VSYNC;
 
-       /* Output data format: CbYCr */
-       reg |= VPU_HDMI_OUTPUT_CBYCR;
+       /* Output data format */
+       reg |= ycrcb_map;
 
        /*
         * Write rate to the async FIFO between VENC and HDMI.
         * One write every 2 wr_clk.
         */
-       if (venc_repeat)
+       if (venc_repeat || yuv420_mode)
                reg |= VPU_HDMI_WR_RATE(2);
 
        /*

diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h
index 1abdcbdf51c088c3130420556c12654b979cec0b..9138255ffc9eeec6aef59964bca8ddc2cc132374 100644 (file)
--- a/drivers/gpu/drm/meson/meson_venc.h
+++ b/drivers/gpu/drm/meson/meson_venc.h
@@ -60,6 +60,8 @@ extern struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc;
 void meson_venci_cvbs_mode_set(struct meson_drm *priv,
                               struct meson_cvbs_enci_mode *mode);
 void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
+                             unsigned int ycrcb_map,
+                             bool yuv420_mode,
                              const struct drm_display_mode *mode);
 unsigned int meson_venci_get_field(struct meson_drm *priv);