drm/amd/display: [FW Promotion] Release 0.0.79

Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index a6f3d58f82c6fc982fb21338a1155d538c0509b7..7b684e7f60dfa0533d9cebbbf0e724ad033574b8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x9b7fa7783
+#define DMUB_FW_VERSION_GIT_HASH 0x7383caadc
 #define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 78
+#define DMUB_FW_VERSION_REVISION 79
 #define DMUB_FW_VERSION_TEST 0
 #define DMUB_FW_VERSION_VBIOS 0
 #define DMUB_FW_VERSION_HOTFIX 0
@@ -322,6 +322,10 @@ union dmub_fw_boot_status {
                uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
                uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
                uint32_t restore_required : 1; /**< 1 if driver should call restore */
+               uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
+               uint32_t reserved : 1;
+               uint32_t detection_required: 1; /**<  if detection need to be triggered by driver */
+
        } bits; /**< status bits */
        uint32_t all; /**< 32-bit access to status bits */
 };
@@ -335,6 +339,7 @@ enum dmub_fw_boot_status_bit {
        DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
        DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
        DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
+       DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
 };
 
 /* Register bit definition for SCRATCH5 */
@@ -489,6 +494,11 @@ enum dmub_gpint_command {
         * RETURN: PSR residency in milli-percent.
         */
        DMUB_GPINT__PSR_RESIDENCY = 9,
+
+       /**
+        * DESC: Notifies DMCUB detection is done so detection required can be cleared.
+        */
+       DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
 };
 
 /**