Merge tag 'riscv-for-linus-5.17-mw0' of git://git.kernel.org/pub/scm/linux/kernel...

Pull RISC-V updates from Palmer Dabbelt:

 - Support for the DA9063 as used on the HiFive Unmatched.

 - Support for relative extables, which puts us in line with other
   architectures and save some space in vmlinux.

 - A handful of kexec fixes/improvements, including the ability to run
   crash kernels from PCI-addressable memory on the HiFive Unmatched.

 - Support for the SBI SRST extension, which allows systems that do not
   have an explicit driver in Linux to reboot.

 - A handful of fixes and cleanups, including to the defconfigs and
   device trees.

* tag 'riscv-for-linus-5.17-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (52 commits)
  RISC-V: Use SBI SRST extension when available
  riscv: mm: fix wrong phys_ram_base value for RV64
  RISC-V: Use common riscv_cpuid_to_hartid_mask() for both SMP=y and SMP=n
  riscv: head: remove useless __PAGE_ALIGNED_BSS and .balign
  riscv: errata: alternative: mark vendor_patch_func __initdata
  riscv: head: make secondary_start_common() static
  riscv: remove cpu_stop()
  riscv: try to allocate crashkern region from 32bit addressible memory
  riscv: use hart id instead of cpu id on machine_kexec
  riscv: Don't use va_pa_offset on kdump
  riscv: dts: sifive: fu540-c000: Fix PLIC node
  riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values
  riscv: dts: sifive: Group tuples in register properties
  riscv: dts: sifive: Group tuples in interrupt properties
  riscv: dts: microchip: mpfs: Group tuples in interrupt properties
  riscv: dts: microchip: mpfs: Fix clock controller node
  riscv: dts: microchip: mpfs: Fix reference clock node
  riscv: dts: microchip: mpfs: Fix PLIC node
  riscv: dts: microchip: mpfs: Drop empty chosen node
  riscv: dts: canaan: Group tuples in interrupt properties
  ...

diff --cc arch/riscv/Kconfig
Simple merge

diff --cc arch/riscv/configs/defconfig
index ef473e2f503b2e1ff6a43f1ac61d1e81a9a80337,56e366d3936e8a50799c351ade0b9b024bf791c4..f120fcc43d0ade00731e15a8074f2a9581a37afa
--- 1/arch/riscv/configs/defconfig
--- 2/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@@ -13,14 -14,12 +14,14 @@@ CONFIG_USER_NS=
  CONFIG_CHECKPOINT_RESTORE=y
  CONFIG_BLK_DEV_INITRD=y
  CONFIG_EXPERT=y
- CONFIG_BPF_SYSCALL=y
+ # CONFIG_SYSFS_SYSCALL is not set
+ CONFIG_SOC_MICROCHIP_POLARFIRE=y
  CONFIG_SOC_SIFIVE=y
  CONFIG_SOC_VIRT=y
- CONFIG_SOC_MICROCHIP_POLARFIRE=y
  CONFIG_SMP=y
  CONFIG_HOTPLUG_CPU=y
 +CONFIG_VIRTUALIZATION=y
 +CONFIG_KVM=m
  CONFIG_JUMP_LABEL=y
  CONFIG_MODULES=y
  CONFIG_MODULE_UNLOAD=y

diff --cc arch/riscv/configs/rv32_defconfig
Simple merge

diff --cc arch/riscv/include/asm/sbi.h
index 9c46dd3ff4a23523563e017ad9d938749487e6e3,289621da4a2a8f62d99d8d808018107b1485e01d..26ba6f2d7a40de9eaf191691ee8f1d0378505077
--- 1/arch/riscv/include/asm/sbi.h
--- 2/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@@ -27,14 -27,7 +27,15 @@@ enum sbi_ext_id 
        SBI_EXT_IPI = 0x735049,
        SBI_EXT_RFENCE = 0x52464E43,
        SBI_EXT_HSM = 0x48534D,
+       SBI_EXT_SRST = 0x53525354,
 +
 +      /* Experimentals extensions must lie within this range */
 +      SBI_EXT_EXPERIMENTAL_START = 0x08000000,
 +      SBI_EXT_EXPERIMENTAL_END = 0x08FFFFFF,
 +
 +      /* Vendor extensions must lie within this range */
 +      SBI_EXT_VENDOR_START = 0x09000000,
 +      SBI_EXT_VENDOR_END = 0x09FFFFFF,
  };
  
  enum sbi_ext_base_fid {

diff --cc arch/riscv/mm/fault.c
Simple merge

diff --cc arch/riscv/net/bpf_jit_comp64.c
Simple merge

diff --cc scripts/sorttable.c
Simple merge