]> git.baikalelectronics.ru Git - kernel.git/commitdiff
arm64: cpufeature: ctr: Fix cpu capability check for late CPUs
authorSuzuki K Poulose <suzuki.poulose@arm.com>
Tue, 9 Oct 2018 13:47:05 +0000 (14:47 +0100)
committerCatalin Marinas <catalin.marinas@arm.com>
Tue, 16 Oct 2018 10:53:28 +0000 (11:53 +0100)
The matches() routine for a capability must honor the "scope"
passed to it and return the proper results.
i.e, when passed with SCOPE_LOCAL_CPU, it should check the
status of the capability on the current CPU. This is used by
verify_local_cpu_capabilities() on a late secondary CPU to make
sure that it's compliant with the established system features.
However, ARM64_HAS_CACHE_{IDC/DIC} always checks the system wide
registers and this could mean that a late secondary CPU could return
"true" (since the CPU hasn't updated the system wide registers yet)
and thus lead the system in an inconsistent state, where
the system assumes it has IDC/DIC feature, while the new CPU
doesn't.

Fixes: commit c3768392b94ed8fce8 ("arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC")
Cc: Philip Elcan <pelcan@codeaurora.org>
Cc: Shanker Donthineni <shankerd@codeaurora.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm64/kernel/cpufeature.c

index 00e7c313f0881c8c0975d1c5070ef3f789ee249a..ba16bb7762ca09faa293f79ec32cd65c58126573 100644 (file)
@@ -854,15 +854,29 @@ static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unus
 }
 
 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
-                         int __unused)
+                         int scope)
 {
-       return read_sanitised_ftr_reg(SYS_CTR_EL0) & BIT(CTR_IDC_SHIFT);
+       u64 ctr;
+
+       if (scope == SCOPE_SYSTEM)
+               ctr = arm64_ftr_reg_ctrel0.sys_val;
+       else
+               ctr = read_cpuid_cachetype();
+
+       return ctr & BIT(CTR_IDC_SHIFT);
 }
 
 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
-                         int __unused)
+                         int scope)
 {
-       return read_sanitised_ftr_reg(SYS_CTR_EL0) & BIT(CTR_DIC_SHIFT);
+       u64 ctr;
+
+       if (scope == SCOPE_SYSTEM)
+               ctr = arm64_ftr_reg_ctrel0.sys_val;
+       else
+               ctr = read_cpuid_cachetype();
+
+       return ctr & BIT(CTR_DIC_SHIFT);
 }
 
 static bool __maybe_unused