drm/amd/display: Update SR watermarks for DCN314

[Why & How]
New values requested by hardware after fine-tuning.
Update for all memory types.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.0.x

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
index 1131c6d73f6cdd2bbfe30a18107428148f34054e..20a06c04e4a1d63f9d710c8f424a67956b154aed 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
@@ -363,32 +363,32 @@ static struct wm_table ddr5_wm_table = {
                        .wm_inst = WM_A,
                        .wm_type = WM_TYPE_PSTATE_CHG,
                        .pstate_latency_us = 11.72,
-                       .sr_exit_time_us = 9,
-                       .sr_enter_plus_exit_time_us = 11,
+                       .sr_exit_time_us = 12.5,
+                       .sr_enter_plus_exit_time_us = 14.5,
                        .valid = true,
                },
                {
                        .wm_inst = WM_B,
                        .wm_type = WM_TYPE_PSTATE_CHG,
                        .pstate_latency_us = 11.72,
-                       .sr_exit_time_us = 9,
-                       .sr_enter_plus_exit_time_us = 11,
+                       .sr_exit_time_us = 12.5,
+                       .sr_enter_plus_exit_time_us = 14.5,
                        .valid = true,
                },
                {
                        .wm_inst = WM_C,
                        .wm_type = WM_TYPE_PSTATE_CHG,
                        .pstate_latency_us = 11.72,
-                       .sr_exit_time_us = 9,
-                       .sr_enter_plus_exit_time_us = 11,
+                       .sr_exit_time_us = 12.5,
+                       .sr_enter_plus_exit_time_us = 14.5,
                        .valid = true,
                },
                {
                        .wm_inst = WM_D,
                        .wm_type = WM_TYPE_PSTATE_CHG,
                        .pstate_latency_us = 11.72,
-                       .sr_exit_time_us = 9,
-                       .sr_enter_plus_exit_time_us = 11,
+                       .sr_exit_time_us = 12.5,
+                       .sr_enter_plus_exit_time_us = 14.5,
                        .valid = true,
                },
        }
@@ -400,32 +400,32 @@ static struct wm_table lpddr5_wm_table = {
                        .wm_inst = WM_A,
                        .wm_type = WM_TYPE_PSTATE_CHG,
                        .pstate_latency_us = 11.65333,
-                       .sr_exit_time_us = 11.5,
-                       .sr_enter_plus_exit_time_us = 14.5,
+                       .sr_exit_time_us = 16.5,
+                       .sr_enter_plus_exit_time_us = 18.5,
                        .valid = true,
                },
                {
                        .wm_inst = WM_B,
                        .wm_type = WM_TYPE_PSTATE_CHG,
                        .pstate_latency_us = 11.65333,
-                       .sr_exit_time_us = 11.5,
-                       .sr_enter_plus_exit_time_us = 14.5,
+                       .sr_exit_time_us = 16.5,
+                       .sr_enter_plus_exit_time_us = 18.5,
                        .valid = true,
                },
                {
                        .wm_inst = WM_C,
                        .wm_type = WM_TYPE_PSTATE_CHG,
                        .pstate_latency_us = 11.65333,
-                       .sr_exit_time_us = 11.5,
-                       .sr_enter_plus_exit_time_us = 14.5,
+                       .sr_exit_time_us = 16.5,
+                       .sr_enter_plus_exit_time_us = 18.5,
                        .valid = true,
                },
                {
                        .wm_inst = WM_D,
                        .wm_type = WM_TYPE_PSTATE_CHG,
                        .pstate_latency_us = 11.65333,
-                       .sr_exit_time_us = 11.5,
-                       .sr_enter_plus_exit_time_us = 14.5,
+                       .sr_exit_time_us = 16.5,
+                       .sr_enter_plus_exit_time_us = 18.5,
                        .valid = true,
                },
        }

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
index cf420ad2b8dcd577b2e1fb28c33f8dcc7b9453d2..34b6c763a455478fc8d17b263f79b3161febb90f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
@@ -146,8 +146,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = {
                },
        },
        .num_states = 5,
-       .sr_exit_time_us = 9.0,
-       .sr_enter_plus_exit_time_us = 11.0,
+       .sr_exit_time_us = 16.5,
+       .sr_enter_plus_exit_time_us = 18.5,
        .sr_exit_z8_time_us = 442.0,
        .sr_enter_plus_exit_z8_time_us = 560.0,
        .writeback_latency_us = 12.0,