#define FSI2SPI_IRQ 0x20
#define SPI_FSI_BASE 0x70000
-#define SPI_FSI_INIT_TIMEOUT_MS 1000
-#define SPI_FSI_STATUS_TIMEOUT_MS 100
+#define SPI_FSI_TIMEOUT_MS 1000
#define SPI_FSI_MAX_RX_SIZE 8
#define SPI_FSI_MAX_TX_SIZE 40
static int fsi_spi_transfer_data(struct fsi_spi *ctx,
struct spi_transfer *transfer)
{
+ int loops;
int rc = 0;
unsigned long end;
u64 status = 0ULL;
if (rc)
return rc;
- end = jiffies + msecs_to_jiffies(SPI_FSI_STATUS_TIMEOUT_MS);
+ loops = 0;
+ end = jiffies + msecs_to_jiffies(SPI_FSI_TIMEOUT_MS);
do {
- if (time_after(jiffies, end))
+ if (loops++ && time_after(jiffies, end))
return -ETIMEDOUT;
rc = fsi_spi_status(ctx, &status, "TX");
u8 *rx = transfer->rx_buf;
while (transfer->len > recv) {
- end = jiffies + msecs_to_jiffies(SPI_FSI_STATUS_TIMEOUT_MS);
+ loops = 0;
+ end = jiffies + msecs_to_jiffies(SPI_FSI_TIMEOUT_MS);
do {
- if (time_after(jiffies, end))
+ if (loops++ && time_after(jiffies, end))
return -ETIMEDOUT;
rc = fsi_spi_status(ctx, &status, "RX");
static int fsi_spi_transfer_init(struct fsi_spi *ctx)
{
+ int loops = 0;
int rc;
bool reset = false;
unsigned long end;
SPI_FSI_CLOCK_CFG_SCK_NO_DEL |
FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 19);
- end = jiffies + msecs_to_jiffies(SPI_FSI_INIT_TIMEOUT_MS);
+ end = jiffies + msecs_to_jiffies(SPI_FSI_TIMEOUT_MS);
do {
- if (time_after(jiffies, end))
+ if (loops++ && time_after(jiffies, end))
return -ETIMEDOUT;
rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, &status);