* @chip_ver: chip silicon revision
* @port_mask: mask of all ports
* @learn_limit_max: maximum number of L2 addresses the chip can learn
- * @cpu: CPU tagging and CPU port configuration for this chip
* @mib_lock: prevent concurrent reads of MIB counters
* @ports: per-port data
* @jam_table: chip-specific initialization jam table
u32 chip_ver;
u32 port_mask;
u32 learn_limit_max;
- struct rtl8365mb_cpu cpu;
struct mutex mib_lock;
struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS];
const struct rtl8365mb_jam_tbl_entry *jam_table;
u32 val;
int ret;
- if (port != priv->cpu_port) {
- dev_err(priv->dev, "only one EXT interface is currently supported\n");
- return -EINVAL;
- }
-
- dp = dsa_to_port(priv->ds, port);
- dn = dp->dn;
-
ext_int = rtl8365mb_extint_port_map[port];
if (ext_int <= 0) {
return -EINVAL;
}
+ dp = dsa_to_port(priv->ds, port);
+ dn = dp->dn;
+
/* Set the RGMII TX/RX delay
*
* The Realtek vendor driver indicates the following possible
int val;
int ret;
- if (port != priv->cpu_port) {
- dev_err(priv->dev, "only one EXT interface is currently supported\n");
- return -EINVAL;
- }
-
ext_int = rtl8365mb_extint_port_map[port];
if (ext_int <= 0) {
static bool rtl8365mb_phy_mode_supported(struct dsa_switch *ds, int port,
phy_interface_t interface)
{
- if (dsa_is_user_port(ds, port) &&
+ int ext_int;
+
+ ext_int = rtl8365mb_extint_port_map[port];
+
+ if (ext_int < 0 &&
(interface == PHY_INTERFACE_MODE_NA ||
interface == PHY_INTERFACE_MODE_INTERNAL ||
interface == PHY_INTERFACE_MODE_GMII))
/* Internal PHY */
return true;
- else if (dsa_is_cpu_port(ds, port) &&
+ else if ((ext_int >= 1) &&
phy_interface_mode_is_rgmii(interface))
/* Extension MAC */
return true;
}
}
-static int rtl8365mb_cpu_config(struct realtek_priv *priv)
+static int rtl8365mb_cpu_config(struct realtek_priv *priv, const struct rtl8365mb_cpu *cpu)
{
- struct rtl8365mb *mb = priv->chip_data;
- struct rtl8365mb_cpu *cpu = &mb->cpu;
u32 val;
int ret;
static int rtl8365mb_setup(struct dsa_switch *ds)
{
struct realtek_priv *priv = ds->priv;
+ struct rtl8365mb_cpu cpu = {0};
struct dsa_port *cpu_dp;
struct rtl8365mb *mb;
int ret;
dev_info(priv->dev, "no interrupt support\n");
/* Configure CPU tagging */
- /* Currently, only one CPU port is supported */
+ cpu.trap_port = RTL8365MB_MAX_NUM_PORTS;
dsa_switch_for_each_cpu_port(cpu_dp, priv->ds) {
- priv->cpu_port = cpu_dp->index;
- mb->cpu.mask = BIT(priv->cpu_port);
- mb->cpu.trap_port = priv->cpu_port;
- ret = rtl8365mb_cpu_config(priv);
- if (ret)
- goto out_teardown_irq;
+ cpu.mask |= BIT(cpu_dp->index);
- break;
+ if (cpu.trap_port == RTL8365MB_MAX_NUM_PORTS)
+ cpu.trap_port = cpu_dp->index;
}
+ cpu.enable = cpu.mask > 0;
+ cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL;
+ cpu.position = RTL8365MB_CPU_POS_AFTER_SA;
+ cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES;
+ cpu.format = RTL8365MB_CPU_FORMAT_8BYTES;
+
+ ret = rtl8365mb_cpu_config(priv, &cpu);
+ if (ret)
+ goto out_teardown_irq;
+
/* Configure ports */
for (i = 0; i < priv->num_ports; i++) {
struct rtl8365mb_port *p = &mb->ports[i];
continue;
/* Forward only to the CPU */
- ret = rtl8365mb_port_set_isolation(priv, i, BIT(priv->cpu_port));
+ ret = rtl8365mb_port_set_isolation(priv, i, cpu.mask);
if (ret)
goto out_teardown_irq;
mb->jam_table = rtl8365mb_init_jam_8365mb_vc;
mb->jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc);
- mb->cpu.enable = 1;
- mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL;
- mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA;
- mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES;
- mb->cpu.format = RTL8365MB_CPU_FORMAT_8BYTES;
-
break;
default:
dev_err(priv->dev,