net: phy: mscc: fix initialization of the MACsec protocol mode

At the very end of the MACsec block initialization in the MSCC PHY
driver, the MACsec "protocol mode" is set. This setting should be set
based on the PHY id within the package, as the bank used to access the
register used depends on this. This was not done correctly, and only the
first bank was used leading to the two upper PHYs being unstable when
using the VSC8584. This patch fixes it.

Fixes: e6a3181c1674 ("net: phy: mscc: macsec initialization")
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h
index 030bf8b600dfeada44de2ed22649e9bf4b07be3c..414e3b31bb1fa77da4680a9ca8829f9bc664adae 100644 (file)
--- a/drivers/net/phy/mscc/mscc.h
+++ b/drivers/net/phy/mscc/mscc.h
@@ -354,6 +354,8 @@ struct vsc8531_private {
        u64 *stats;
        int nstats;
        bool pkg_init;
+       /* PHY address within the package. */
+       u8 addr;
        /* For multiple port PHYs; the MDIO address of the base PHY in the
         * package.
         */

diff --git a/drivers/net/phy/mscc/mscc_mac.h b/drivers/net/phy/mscc/mscc_mac.h
index fcb5ba5e5d033c8a3ae66673337fa9f16d6c0b15..59b6837c60b3123c255794d226ef71f51322a0c8 100644 (file)
--- a/drivers/net/phy/mscc/mscc_mac.h
+++ b/drivers/net/phy/mscc/mscc_mac.h
@@ -152,8 +152,8 @@
 #define MSCC_MAC_PAUSE_CFG_STATE_PAUSE_STATE                   BIT(0)
 #define MSCC_MAC_PAUSE_CFG_STATE_MAC_TX_PAUSE_GEN              BIT(4)
 
-#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL                      0x2
-#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(x)     (x)
-#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M      GENMASK(2, 0)
+#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL                        0x2
+#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(x)       (x)
+#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M        GENMASK(2, 0)
 
 #endif /* _MSCC_PHY_LINE_MAC_H_ */

diff --git a/drivers/net/phy/mscc/mscc_macsec.c b/drivers/net/phy/mscc/mscc_macsec.c
index e99e2cd72a0c413f1109bd819cc1d60e4468a792..b4d3dc4068e279c45e6499b4ce4b0de406c92646 100644 (file)
--- a/drivers/net/phy/mscc/mscc_macsec.c
+++ b/drivers/net/phy/mscc/mscc_macsec.c
@@ -316,6 +316,8 @@ static void vsc8584_macsec_mac_init(struct phy_device *phydev,
 /* Must be called with mdio_lock taken */
 static int __vsc8584_macsec_init(struct phy_device *phydev)
 {
+       struct vsc8531_private *priv = phydev->priv;
+       enum macsec_bank proc_bank;
        u32 val;
 
        vsc8584_macsec_block_init(phydev, MACSEC_INGR);
@@ -351,12 +353,14 @@ static int __vsc8584_macsec_init(struct phy_device *phydev)
        val |= MSCC_FCBUF_ENA_CFG_TX_ENA | MSCC_FCBUF_ENA_CFG_RX_ENA;
        vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG, val);
 
-       val = vsc8584_macsec_phy_read(phydev, IP_1588,
-                                     MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL);
-       val &= ~MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M;
-       val |= MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(4);
-       vsc8584_macsec_phy_write(phydev, IP_1588,
-                                MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL, val);
+       proc_bank = (priv->addr < 2) ? PROC_0 : PROC_2;
+
+       val = vsc8584_macsec_phy_read(phydev, proc_bank,
+                                     MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL);
+       val &= ~MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M;
+       val |= MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(4);
+       vsc8584_macsec_phy_write(phydev, proc_bank,
+                                MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL, val);
 
        return 0;
 }

diff --git a/drivers/net/phy/mscc/mscc_macsec.h b/drivers/net/phy/mscc/mscc_macsec.h
index d0783944d106873caf2fef5faf974c900b04d22b..d751f2946b7926bc310fa7819eae61fe5465d286 100644 (file)
--- a/drivers/net/phy/mscc/mscc_macsec.h
+++ b/drivers/net/phy/mscc/mscc_macsec.h
@@ -64,7 +64,8 @@ enum macsec_bank {
        FC_BUFFER   = 0x04,
        HOST_MAC    = 0x05,
        LINE_MAC    = 0x06,
-       IP_1588     = 0x0e,
+       PROC_0      = 0x0e,
+       PROC_2      = 0x0f,
        MACSEC_INGR = 0x38,
        MACSEC_EGR  = 0x3c,
 };

diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c
index acddef79f4e8d5df07962215843326a9b438085c..c8aa6d905d8e63759782153cd58d26e3bf40157f 100644 (file)
--- a/drivers/net/phy/mscc/mscc_main.c
+++ b/drivers/net/phy/mscc/mscc_main.c
@@ -1347,6 +1347,8 @@ static int vsc8584_config_init(struct phy_device *phydev)
        else
                vsc8531->base_addr = phydev->mdio.addr - addr;
 
+       vsc8531->addr = addr;
+
        /* Some parts of the init sequence are identical for every PHY in the
         * package. Some parts are modifying the GPIO register bank which is a
         * set of registers that are affecting all PHYs, a few resetting the
@@ -1771,6 +1773,8 @@ static int vsc8514_config_init(struct phy_device *phydev)
        else
                vsc8531->base_addr = phydev->mdio.addr - addr;
 
+       vsc8531->addr = addr;
+
        /* Some parts of the init sequence are identical for every PHY in the
         * package. Some parts are modifying the GPIO register bank which is a
         * set of registers that are affecting all PHYs, a few resetting the