clk: renesas: Add dummy SDnH clock

Currently, SDnH is handled together with SDn. This caused lots of
problems, so we want SDnH as a separate clock. Introduce a dummy SDnH
type here which creates a fixed-factor clock with factor 1. That allows
us to convert the per-SoC CPG drivers while keeping the old behaviour
for now. A later patch then will add the proper functionality.

Based on Linux series by Wolfram Sang:
commit a31cf51bf6b4b ("clk: renesas: rcar-gen3: Add dummy SDnH clock"),
commit 1abd04480866c ("clk: renesas: rcar-gen3: Add SDnH clock"),
commit 63494b6f98f26 ("clk: renesas: r8a779a0: Add SDnH clock to V3U")

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Switch to gen3_clk_get_rate64

diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index bcf5865222f3930883780b405800c5818b67f389..84cf072cae6c671a3895823679f9a9f02b05d95f 100644 (file)
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -289,6 +289,9 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
                      div, rate);
                return rate;
 
+       case CLK_TYPE_GEN3_SDH: /* Fixed factor 1:1 */
+               return gen3_clk_get_rate64(&parent);
+
        case CLK_TYPE_GEN3_SD:          /* FIXME */
                fallthrough;
        case CLK_TYPE_R8A779A0_SD:

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 7bf57013619a7800d2bde0eab5186a3e7b3a5764..9ca42c2dddbf9e82db91a320207f132a262b7d50 100644 (file)
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -17,6 +17,7 @@ enum rcar_gen3_clk_types {
        CLK_TYPE_GEN3_PLL2,
        CLK_TYPE_GEN3_PLL3,
        CLK_TYPE_GEN3_PLL4,
+       CLK_TYPE_GEN3_SDH,
        CLK_TYPE_GEN3_SD,
        CLK_TYPE_GEN3_R,
        CLK_TYPE_GEN3_MDSEL,    /* Select parent/divider using mode pin */
@@ -40,6 +41,9 @@ enum rcar_gen3_clk_types {
        CLK_TYPE_GEN3_SOC_BASE,
 };
 
+#define DEF_GEN3_SDH(_name, _id, _parent, _offset)     \
+       DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
+
 #define DEF_GEN3_SD(_name, _id, _parent, _offset)      \
        DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)