drm: msm: a6xx: send opp instead of a frequency

This patch changes the plumbing to send the devfreq recommended opp rather
than the frequency. Also consolidate and rearrange the code in a6xx to set
the GPU frequency and the icc vote in preparation for the upcoming
changes for GPU->DDR scaling votes.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 21e77d67151f58041f69ed776a5e31ee521ab020..856db46e93c4a6a44ae14ee684cd5cf2203f752e 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -103,17 +103,45 @@ bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
                A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
 }
 
-static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
+void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
 {
-       struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
-       struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
-       struct msm_gpu *gpu = &adreno_gpu->base;
-       int ret;
+       struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+       struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
+       struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
+       u32 perf_index;
+       unsigned long gpu_freq;
+       int ret = 0;
+
+       gpu_freq = dev_pm_opp_get_freq(opp);
+
+       if (gpu_freq == gmu->freq)
+               return;
+
+       for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
+               if (gpu_freq == gmu->gpu_freqs[perf_index])
+                       break;
+
+       gmu->current_perf_index = perf_index;
+       gmu->freq = gmu->gpu_freqs[perf_index];
+
+       /*
+        * This can get called from devfreq while the hardware is idle. Don't
+        * bring up the power if it isn't already active
+        */
+       if (pm_runtime_get_if_in_use(gmu->dev) == 0)
+               return;
+
+       if (!gmu->legacy) {
+               a6xx_hfi_set_freq(gmu, perf_index);
+               icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));
+               pm_runtime_put(gmu->dev);
+               return;
+       }
 
        gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
 
        gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
-               ((3 & 0xf) << 28) | index);
+                       ((3 & 0xf) << 28) | perf_index);
 
        /*
         * Send an invalid index as a vote for the bus bandwidth and let the
@@ -134,37 +162,6 @@ static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
         * for now leave it at max so that the performance is nominal.
         */
        icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));
-}
-
-void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq)
-{
-       struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
-       struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
-       struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
-       u32 perf_index = 0;
-
-       if (freq == gmu->freq)
-               return;
-
-       for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
-               if (freq == gmu->gpu_freqs[perf_index])
-                       break;
-
-       gmu->current_perf_index = perf_index;
-       gmu->freq = gmu->gpu_freqs[perf_index];
-
-       /*
-        * This can get called from devfreq while the hardware is idle. Don't
-        * bring up the power if it isn't already active
-        */
-       if (pm_runtime_get_if_in_use(gmu->dev) == 0)
-               return;
-
-       if (gmu->legacy)
-               __a6xx_gmu_set_freq(gmu, perf_index);
-       else
-               a6xx_hfi_set_freq(gmu, perf_index);
-
        pm_runtime_put(gmu->dev);
 }
 
@@ -839,6 +836,19 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
        a6xx_gmu_rpmh_off(gmu);
 }
 
+static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
+{
+       struct dev_pm_opp *gpu_opp;
+       unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
+
+       gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
+       if (IS_ERR_OR_NULL(gpu_opp))
+               return;
+
+       a6xx_gmu_set_freq(gpu, gpu_opp);
+       dev_pm_opp_put(gpu_opp);
+}
+
 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
 {
        struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
@@ -898,10 +908,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
        enable_irq(gmu->hfi_irq);
 
        /* Set the GPU to the current freq */
-       if (gmu->legacy)
-               __a6xx_gmu_set_freq(gmu, gmu->current_perf_index);
-       else
-               a6xx_hfi_set_freq(gmu, gmu->current_perf_index);
+       a6xx_gmu_set_initial_freq(gpu, gmu);
 
        /*
         * "enable" the GX power domain which won't actually do anything but it

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index 7239b8b6093994d2dac5796f207118afaeefe6f8..03ba60d5b07f84a2cec9c75a29a67fdcd61c6132 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -63,7 +63,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu);
 
-void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq);
+void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp);
 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu);
 
 void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,

diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 3763d40026293ccb27d8902d8fc179570a075302..d5645472b25da4a1f445ea2316f5c35ac0f01201 100644 (file)
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -13,7 +13,6 @@
 
 #include <generated/utsrelease.h>
 #include <linux/string_helpers.h>
-#include <linux/pm_opp.h>
 #include <linux/devfreq.h>
 #include <linux/devcoredump.h>
 #include <linux/sched/task.h>
@@ -34,7 +33,7 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq,
                return PTR_ERR(opp);
 
        if (gpu->funcs->gpu_set_freq)
-               gpu->funcs->gpu_set_freq(gpu, (u64)*freq);
+               gpu->funcs->gpu_set_freq(gpu, opp);
        else
                clk_set_rate(gpu->core_clk, *freq);
 

diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 429cb40f793150426fb00a21b96a5ab39762dab4..0db117a7339b6959a979a31ccbd4f2b3b0adcc9f 100644 (file)
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -9,6 +9,7 @@
 
 #include <linux/clk.h>
 #include <linux/interconnect.h>
+#include <linux/pm_opp.h>
 #include <linux/regulator/consumer.h>
 
 #include "msm_drv.h"
@@ -61,7 +62,7 @@ struct msm_gpu_funcs {
        struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
        int (*gpu_state_put)(struct msm_gpu_state *state);
        unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
-       void (*gpu_set_freq)(struct msm_gpu *gpu, unsigned long freq);
+       void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp);
        struct msm_gem_address_space *(*create_address_space)
                (struct msm_gpu *gpu, struct platform_device *pdev);
 };