fix(xilinx): initialize values to device enum members

Initialized values explicitly to device enum members to avoid
value assignment from the compiler and for better readability.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I20f24c3b4fb47b2b011def9f1f43ea8238c66b80

diff --git a/plat/xilinx/common/include/pm_node.h b/plat/xilinx/common/include/pm_node.h
index 371c72d7e536ee803f9829790f31f1d269e1b9f4..97303672fabef464678823677ad51ea576be33d0 100644 (file)
--- a/plat/xilinx/common/include/pm_node.h
+++ b/plat/xilinx/common/include/pm_node.h
@@ -85,109 +85,109 @@ enum pm_device_node_type {
 /* Device node Indexes */
 enum pm_device_node_idx {
        /* Device nodes */
-       XPM_NODEIDX_DEV_MIN,
+       XPM_NODEIDX_DEV_MIN = 0x0,
 
        /* Processor devices */
-       XPM_NODEIDX_DEV_PMC_PROC,
-       XPM_NODEIDX_DEV_PSM_PROC,
-       XPM_NODEIDX_DEV_ACPU_0,
-       XPM_NODEIDX_DEV_ACPU_1,
-       XPM_NODEIDX_DEV_RPU0_0,
-       XPM_NODEIDX_DEV_RPU0_1,
+       XPM_NODEIDX_DEV_PMC_PROC = 0x1,
+       XPM_NODEIDX_DEV_PSM_PROC = 0x2,
+       XPM_NODEIDX_DEV_ACPU_0 = 0x3,
+       XPM_NODEIDX_DEV_ACPU_1 = 0x4,
+       XPM_NODEIDX_DEV_RPU0_0 = 0x5,
+       XPM_NODEIDX_DEV_RPU0_1 = 0x6,
 
        /* Memory devices */
-       XPM_NODEIDX_DEV_OCM_0,
-       XPM_NODEIDX_DEV_OCM_1,
-       XPM_NODEIDX_DEV_OCM_2,
-       XPM_NODEIDX_DEV_OCM_3,
-       XPM_NODEIDX_DEV_TCM_0_A,
-       XPM_NODEIDX_DEV_TCM_0_B,
-       XPM_NODEIDX_DEV_TCM_1_A,
-       XPM_NODEIDX_DEV_TCM_1_B,
-       XPM_NODEIDX_DEV_L2_BANK_0,
-       XPM_NODEIDX_DEV_DDR_0,
-       XPM_NODEIDX_DEV_DDR_1,
-       XPM_NODEIDX_DEV_DDR_2,
-       XPM_NODEIDX_DEV_DDR_3,
-       XPM_NODEIDX_DEV_DDR_4,
-       XPM_NODEIDX_DEV_DDR_5,
-       XPM_NODEIDX_DEV_DDR_6,
-       XPM_NODEIDX_DEV_DDR_7,
+       XPM_NODEIDX_DEV_OCM_0 = 0x7,
+       XPM_NODEIDX_DEV_OCM_1 = 0x8,
+       XPM_NODEIDX_DEV_OCM_2 = 0x9,
+       XPM_NODEIDX_DEV_OCM_3 = 0xA,
+       XPM_NODEIDX_DEV_TCM_0_A = 0xB,
+       XPM_NODEIDX_DEV_TCM_0_B = 0xC,
+       XPM_NODEIDX_DEV_TCM_1_A = 0xD,
+       XPM_NODEIDX_DEV_TCM_1_B = 0xE,
+       XPM_NODEIDX_DEV_L2_BANK_0 = 0xF,
+       XPM_NODEIDX_DEV_DDR_0 = 0x10,
+       XPM_NODEIDX_DEV_DDR_1 = 0x11,
+       XPM_NODEIDX_DEV_DDR_2 = 0x12,
+       XPM_NODEIDX_DEV_DDR_3 = 0x13,
+       XPM_NODEIDX_DEV_DDR_4 = 0x14,
+       XPM_NODEIDX_DEV_DDR_5 = 0x15,
+       XPM_NODEIDX_DEV_DDR_6 = 0x16,
+       XPM_NODEIDX_DEV_DDR_7 = 0x17,
 
        /* LPD Peripheral devices */
-       XPM_NODEIDX_DEV_USB_0,
-       XPM_NODEIDX_DEV_GEM_0,
-       XPM_NODEIDX_DEV_GEM_1,
-       XPM_NODEIDX_DEV_SPI_0,
-       XPM_NODEIDX_DEV_SPI_1,
-       XPM_NODEIDX_DEV_I2C_0,
-       XPM_NODEIDX_DEV_I2C_1,
-       XPM_NODEIDX_DEV_CAN_FD_0,
-       XPM_NODEIDX_DEV_CAN_FD_1,
-       XPM_NODEIDX_DEV_UART_0,
-       XPM_NODEIDX_DEV_UART_1,
-       XPM_NODEIDX_DEV_GPIO,
-       XPM_NODEIDX_DEV_TTC_0,
-       XPM_NODEIDX_DEV_TTC_1,
-       XPM_NODEIDX_DEV_TTC_2,
-       XPM_NODEIDX_DEV_TTC_3,
-       XPM_NODEIDX_DEV_SWDT_LPD,
+       XPM_NODEIDX_DEV_USB_0 = 0x18,
+       XPM_NODEIDX_DEV_GEM_0 = 0x19,
+       XPM_NODEIDX_DEV_GEM_1 = 0x1A,
+       XPM_NODEIDX_DEV_SPI_0 = 0x1B,
+       XPM_NODEIDX_DEV_SPI_1 = 0x1C,
+       XPM_NODEIDX_DEV_I2C_0 = 0x1D,
+       XPM_NODEIDX_DEV_I2C_1 = 0x1E,
+       XPM_NODEIDX_DEV_CAN_FD_0 = 0x1F,
+       XPM_NODEIDX_DEV_CAN_FD_1 = 0x20,
+       XPM_NODEIDX_DEV_UART_0 = 0x21,
+       XPM_NODEIDX_DEV_UART_1 = 0x22,
+       XPM_NODEIDX_DEV_GPIO = 0x23,
+       XPM_NODEIDX_DEV_TTC_0 = 0x24,
+       XPM_NODEIDX_DEV_TTC_1 = 0x25,
+       XPM_NODEIDX_DEV_TTC_2 = 0x26,
+       XPM_NODEIDX_DEV_TTC_3 = 0x27,
+       XPM_NODEIDX_DEV_SWDT_LPD = 0x28,
 
        /* FPD Peripheral devices */
-       XPM_NODEIDX_DEV_SWDT_FPD,
+       XPM_NODEIDX_DEV_SWDT_FPD = 0x29,
 
        /* PMC Peripheral devices */
-       XPM_NODEIDX_DEV_OSPI,
-       XPM_NODEIDX_DEV_QSPI,
-       XPM_NODEIDX_DEV_GPIO_PMC,
-       XPM_NODEIDX_DEV_I2C_PMC,
-       XPM_NODEIDX_DEV_SDIO_0,
-       XPM_NODEIDX_DEV_SDIO_1,
-
-       XPM_NODEIDX_DEV_PL_0,
-       XPM_NODEIDX_DEV_PL_1,
-       XPM_NODEIDX_DEV_PL_2,
-       XPM_NODEIDX_DEV_PL_3,
-       XPM_NODEIDX_DEV_RTC,
-       XPM_NODEIDX_DEV_ADMA_0,
-       XPM_NODEIDX_DEV_ADMA_1,
-       XPM_NODEIDX_DEV_ADMA_2,
-       XPM_NODEIDX_DEV_ADMA_3,
-       XPM_NODEIDX_DEV_ADMA_4,
-       XPM_NODEIDX_DEV_ADMA_5,
-       XPM_NODEIDX_DEV_ADMA_6,
-       XPM_NODEIDX_DEV_ADMA_7,
-       XPM_NODEIDX_DEV_IPI_0,
-       XPM_NODEIDX_DEV_IPI_1,
-       XPM_NODEIDX_DEV_IPI_2,
-       XPM_NODEIDX_DEV_IPI_3,
-       XPM_NODEIDX_DEV_IPI_4,
-       XPM_NODEIDX_DEV_IPI_5,
-       XPM_NODEIDX_DEV_IPI_6,
+       XPM_NODEIDX_DEV_OSPI = 0x2A,
+       XPM_NODEIDX_DEV_QSPI = 0x2B,
+       XPM_NODEIDX_DEV_GPIO_PMC = 0x2C,
+       XPM_NODEIDX_DEV_I2C_PMC = 0x2D,
+       XPM_NODEIDX_DEV_SDIO_0 = 0x2E,
+       XPM_NODEIDX_DEV_SDIO_1 = 0x2F,
+
+       XPM_NODEIDX_DEV_PL_0 = 0x30,
+       XPM_NODEIDX_DEV_PL_1 = 0x31,
+       XPM_NODEIDX_DEV_PL_2 = 0x32,
+       XPM_NODEIDX_DEV_PL_3 = 0x33,
+       XPM_NODEIDX_DEV_RTC = 0x34,
+       XPM_NODEIDX_DEV_ADMA_0 = 0x35,
+       XPM_NODEIDX_DEV_ADMA_1 = 0x36,
+       XPM_NODEIDX_DEV_ADMA_2 = 0x37,
+       XPM_NODEIDX_DEV_ADMA_3 = 0x38,
+       XPM_NODEIDX_DEV_ADMA_4 = 0x39,
+       XPM_NODEIDX_DEV_ADMA_5 = 0x3A,
+       XPM_NODEIDX_DEV_ADMA_6 = 0x3B,
+       XPM_NODEIDX_DEV_ADMA_7 = 0x3C,
+       XPM_NODEIDX_DEV_IPI_0 = 0x3D,
+       XPM_NODEIDX_DEV_IPI_1 = 0x3E,
+       XPM_NODEIDX_DEV_IPI_2 = 0x3F,
+       XPM_NODEIDX_DEV_IPI_3 = 0x40,
+       XPM_NODEIDX_DEV_IPI_4 = 0x41,
+       XPM_NODEIDX_DEV_IPI_5 = 0x42,
+       XPM_NODEIDX_DEV_IPI_6 = 0x43,
 
        /* Entire SoC */
-       XPM_NODEIDX_DEV_SOC,
+       XPM_NODEIDX_DEV_SOC = 0x44,
 
        /* DDR memory controllers */
-       XPM_NODEIDX_DEV_DDRMC_0,
-       XPM_NODEIDX_DEV_DDRMC_1,
-       XPM_NODEIDX_DEV_DDRMC_2,
-       XPM_NODEIDX_DEV_DDRMC_3,
+       XPM_NODEIDX_DEV_DDRMC_0 = 0x45,
+       XPM_NODEIDX_DEV_DDRMC_1 = 0x46,
+       XPM_NODEIDX_DEV_DDRMC_2 = 0x47,
+       XPM_NODEIDX_DEV_DDRMC_3 = 0x48,
 
        /* GT devices */
-       XPM_NODEIDX_DEV_GT_0,
-       XPM_NODEIDX_DEV_GT_1,
-       XPM_NODEIDX_DEV_GT_2,
-       XPM_NODEIDX_DEV_GT_3,
-       XPM_NODEIDX_DEV_GT_4,
-       XPM_NODEIDX_DEV_GT_5,
-       XPM_NODEIDX_DEV_GT_6,
-       XPM_NODEIDX_DEV_GT_7,
-       XPM_NODEIDX_DEV_GT_8,
-       XPM_NODEIDX_DEV_GT_9,
-       XPM_NODEIDX_DEV_GT_10,
-
-       XPM_NODEIDX_DEV_MAX
+       XPM_NODEIDX_DEV_GT_0 = 0x49,
+       XPM_NODEIDX_DEV_GT_1 = 0x4A,
+       XPM_NODEIDX_DEV_GT_2 = 0x4B,
+       XPM_NODEIDX_DEV_GT_3 = 0x4C,
+       XPM_NODEIDX_DEV_GT_4 = 0x4D,
+       XPM_NODEIDX_DEV_GT_5 = 0x4E,
+       XPM_NODEIDX_DEV_GT_6 = 0x4F,
+       XPM_NODEIDX_DEV_GT_7 = 0x50,
+       XPM_NODEIDX_DEV_GT_8 = 0x51,
+       XPM_NODEIDX_DEV_GT_9 = 0x52,
+       XPM_NODEIDX_DEV_GT_10 = 0x53,
+
+       XPM_NODEIDX_DEV_MAX = 0x54,
 };
 
 #endif /* PM_NODE_H */