soc: mediatek: pwrap: add pwrap driver for mt6765 SoCs

mt6765 is a highly integrated SoCs, it uses mt6357 for power management.
This patch adds pwrap driver to access mt6357. Pwrap of mt6765 support
dynamic priority meichanism, sequence monitor and starvation mechanism
to make transaction more reliable.

Signed-off-by: Argus Lin <argus.lin@mediatek.com>
[mb: change has_bridge to capabilities]
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index 308fda08654be9dfdd08d17d6f829349261f41bd..74c86d0cf1fbb16c00335df835f72e75cbea7a0c 100644 (file)
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -454,6 +454,38 @@ static int mt2701_regs[] = {
        [PWRAP_ADC_RDATA_ADDR2] =       0x154,
 };
 
+static int mt6765_regs[] = {
+       [PWRAP_MUX_SEL] =               0x0,
+       [PWRAP_WRAP_EN] =               0x4,
+       [PWRAP_DIO_EN] =                0x8,
+       [PWRAP_RDDMY] =                 0x20,
+       [PWRAP_CSHEXT_WRITE] =          0x24,
+       [PWRAP_CSHEXT_READ] =           0x28,
+       [PWRAP_CSLEXT_START] =          0x2C,
+       [PWRAP_CSLEXT_END] =            0x30,
+       [PWRAP_STAUPD_PRD] =            0x3C,
+       [PWRAP_HARB_HPRIO] =            0x68,
+       [PWRAP_HIPRIO_ARB_EN] =         0x6C,
+       [PWRAP_MAN_EN] =                0x7C,
+       [PWRAP_MAN_CMD] =               0x80,
+       [PWRAP_WACS0_EN] =              0x8C,
+       [PWRAP_WACS1_EN] =              0x94,
+       [PWRAP_WACS2_EN] =              0x9C,
+       [PWRAP_INIT_DONE2] =            0xA0,
+       [PWRAP_WACS2_CMD] =             0xC20,
+       [PWRAP_WACS2_RDATA] =           0xC24,
+       [PWRAP_WACS2_VLDCLR] =          0xC28,
+       [PWRAP_INT_EN] =                0xB4,
+       [PWRAP_INT_FLG_RAW] =           0xB8,
+       [PWRAP_INT_FLG] =               0xBC,
+       [PWRAP_INT_CLR] =               0xC0,
+       [PWRAP_TIMER_EN] =              0xE8,
+       [PWRAP_WDT_UNIT] =              0xF0,
+       [PWRAP_WDT_SRC_EN] =            0xF4,
+       [PWRAP_DCM_EN] =                0x1DC,
+       [PWRAP_DCM_DBC_PRD] =           0x1E0,
+};
+
 static int mt6797_regs[] = {
        [PWRAP_MUX_SEL] =               0x0,
        [PWRAP_WRAP_EN] =               0x4,
@@ -815,6 +847,7 @@ enum pmic_type {
 
 enum pwrap_type {
        PWRAP_MT2701,
+       PWRAP_MT6765,
        PWRAP_MT6797,
        PWRAP_MT7622,
        PWRAP_MT8135,
@@ -1245,6 +1278,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
                pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
                break;
        case PWRAP_MT2701:
+       case PWRAP_MT6765:
        case PWRAP_MT6797:
        case PWRAP_MT8173:
                pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
@@ -1624,6 +1658,18 @@ static const struct pmic_wrapper_type pwrap_mt2701 = {
        .init_soc_specific = pwrap_mt2701_init_soc_specific,
 };
 
+static const struct pmic_wrapper_type pwrap_mt6765 = {
+       .regs = mt6765_regs,
+       .type = PWRAP_MT6765,
+       .arb_en_all = 0x3fd35,
+       .int_en_all = 0xffffffff,
+       .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
+       .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
+       .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
+       .init_reg_clock = pwrap_common_init_reg_clock,
+       .init_soc_specific = NULL,
+};
+
 static const struct pmic_wrapper_type pwrap_mt6797 = {
        .regs = mt6797_regs,
        .type = PWRAP_MT6797,
@@ -1693,6 +1739,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
        {
                .compatible = "mediatek,mt2701-pwrap",
                .data = &pwrap_mt2701,
+       }, {
+               .compatible = "mediatek,mt6765-pwrap",
+               .data = &pwrap_mt6765,
        }, {
                .compatible = "mediatek,mt6797-pwrap",
                .data = &pwrap_mt6797,