]> git.baikalelectronics.ru Git - uboot.git/commitdiff
rockchip: rk3568: enable automatic power savings
authorChris Morgan <macromorgan@hotmail.com>
Mon, 13 Feb 2023 22:27:39 +0000 (16:27 -0600)
committerKever Yang <kever.yang@rock-chips.com>
Tue, 28 Feb 2023 10:07:27 +0000 (18:07 +0800)
It enables automatic clock gating on idle, disables the eDP phy by
default, and sets the core pvtpll ring length. It is reported this
lowers the temperature on at least one SoC by 7C.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
arch/arm/mach-rockchip/rk3568/rk3568.c

index a2d59abc265d167dee4a148e9fabe2a95527cb98..4a08820a0937a3f99591ce44ca998ecd44b436e3 100644 (file)
 #define SGRF_SOC_CON4                  0x10
 #define EMMC_HPROT_SECURE_CTRL         0x03
 #define SDMMC0_HPROT_SECURE_CTRL       0x01
+
+#define PMU_BASE_ADDR          0xfdd90000
+#define PMU_NOC_AUTO_CON0      (0x70)
+#define PMU_NOC_AUTO_CON1      (0x74)
+#define EDP_PHY_GRF_BASE       0xfdcb0000
+#define EDP_PHY_GRF_CON0       (EDP_PHY_GRF_BASE + 0x00)
+#define EDP_PHY_GRF_CON10      (EDP_PHY_GRF_BASE + 0x28)
+#define CPU_GRF_BASE           0xfdc30000
+#define GRF_CORE_PVTPLL_CON0   (0x10)
+
 /* PMU_GRF_GPIO0D_IOMUX_L */
 enum {
        GPIO0D1_SHIFT           = 4,
@@ -98,6 +108,20 @@ void board_debug_uart_init(void)
 int arch_cpu_init(void)
 {
 #ifdef CONFIG_SPL_BUILD
+       /*
+        * When perform idle operation, corresponding clock can
+        * be opened or gated automatically.
+        */
+       writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
+       writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
+
+       /* Disable eDP phy by default */
+       writel(0x00070007, EDP_PHY_GRF_CON10);
+       writel(0x0ff10ff1, EDP_PHY_GRF_CON0);
+
+       /* Set core pvtpll ring length */
+       writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0);
+
        /* Set the emmc sdmmc0 to secure */
        rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
                | SDMMC0_HPROT_SECURE_CTRL << 4));