drm/i915: Power well id for ICL PG3

Gen11 onwards PG3 is contains functions for pipe B,
external displays, and VGA. It make sense to add
a power well id with name ICL_DISP_PW_3 rather then
TGL_DISP_PW_3, Also PG3 power well id requires to
know if lpsp is enabled.

Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200415170555.15531-2-anshuman.gupta@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 03bdde19c8c9e52f90848e7363a31586e4deac95..1d01c79fb9dbbaada15413408df337a5cbabdd06 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -943,7 +943,7 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 
        /* Power wells at this level and above must be disabled for DC5 entry */
        if (INTEL_GEN(dev_priv) >= 12)
-               high_pg = TGL_DISP_PW_3;
+               high_pg = ICL_DISP_PW_3;
        else
                high_pg = SKL_DISP_PW_2;
 
@@ -3571,7 +3571,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
                .name = "power well 3",
                .domains = ICL_PW_3_POWER_DOMAINS,
                .ops = &hsw_power_well_ops,
-               .id = DISP_PW_ID_NONE,
+               .id = ICL_DISP_PW_3,
                {
                        .hsw.regs = &hsw_power_well_regs,
                        .hsw.idx = ICL_PW_CTL_IDX_PW_3,
@@ -3949,7 +3949,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
                .name = "power well 3",
                .domains = TGL_PW_3_POWER_DOMAINS,
                .ops = &hsw_power_well_ops,
-               .id = TGL_DISP_PW_3,
+               .id = ICL_DISP_PW_3,
                {
                        .hsw.regs = &hsw_power_well_regs,
                        .hsw.idx = ICL_PW_CTL_IDX_PW_3,

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index da64a5edae7ad14c75f3519bc14771ea8bf8f141..56cbae6327b72c58190f0294374a9dd93051f0d7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -100,7 +100,7 @@ enum i915_power_well_id {
        SKL_DISP_PW_MISC_IO,
        SKL_DISP_PW_1,
        SKL_DISP_PW_2,
-       TGL_DISP_PW_3,
+       ICL_DISP_PW_3,
        SKL_DISP_DC_OFF,
 };