drm/amdgpu: use queue 0 for kiq ring

It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN only can be issued on
queue 0.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index bb40d2529a307eb9f71973e1d0628e3766da984c..239bf2a4b3c68be7bfd09510a7196e1967cd8326 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -179,8 +179,12 @@ static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
 
                amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue);
 
-               /* Using pipes 2/3 from MEC 2 seems cause problems */
-               if (mec == 1 && pipe > 1)
+               /*
+                * 1. Using pipes 2/3 from MEC 2 seems cause problems.
+                * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
+                * only can be issued on queue 0.
+                */
+               if ((mec == 1 && pipe > 1) || queue != 0)
                        continue;
 
                ring->me = mec + 1;