KVM: x86: add support for CPUID leaf 0x80000021

CPUID leaf 0x80000021 defines some features (or lack of bugs) of AMD
processors.  Expose the ones that make sense via KVM_GET_SUPPORTED_CPUID.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index afcdd4e693e510d912b42a9dfa741461b97e7dc8..f0d5ac7a12c9228dc92e7e1fcb320eba36784a7f 100644 (file)
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1068,7 +1068,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
                entry->edx = 0;
                break;
        case 0x80000000:
-               entry->eax = min(entry->eax, 0x8000001f);
+               entry->eax = min(entry->eax, 0x80000021);
                break;
        case 0x80000001:
                cpuid_entry_override(entry, CPUID_8000_0001_EDX);
@@ -1139,6 +1139,23 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
                        entry->ebx &= ~GENMASK(11, 6);
                }
                break;
+       case 0x80000020:
+               entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
+               break;
+       case 0x80000021:
+               entry->ebx = entry->ecx = entry->edx = 0;
+               /*
+                * Pass down these bits:
+                *    EAX      0      NNDBP, Processor ignores nested data breakpoints
+                *    EAX      2      LAS, LFENCE always serializing
+                *    EAX      6      NSCB, Null selector clear base
+                *
+                * Other defined bits are for MSRs that KVM does not expose:
+                *   EAX      3      SPCL, SMM page configuration lock
+                *   EAX      13     PCMSR, Prefetch control MSR
+                */
+               entry->eax &= BIT(0) | BIT(2) | BIT(6);
+               break;
        /*Add support for Centaur's CPUID instruction*/
        case 0xC0000000:
                /*Just support up to 0xC0000004 now*/