rtw88: 8822c: update channel and bandwidth BB setting

In 2G channels, the cck source and rxagc should be set to different
values based on different bandwidth to increase the performance of rx
sensitivity.

To improve rx throughput performance, the values of sbd subtune and
pt_opt should be changed in different bandwidth.

Signed-off-by: Chien-Hsun Liao <ben.liao@realtek.com>
Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>

diff --git a/drivers/net/wireless/realtek/rtw88/rtw8822c.c b/drivers/net/wireless/realtek/rtw88/rtw8822c.c
index b4f7242e5aa312a74f1a5d969acde829dfffcf71..be46a1bde46e5523eb11dac494c7dae726a2deab 100644 (file)
--- a/drivers/net/wireless/realtek/rtw88/rtw8822c.c
+++ b/drivers/net/wireless/realtek/rtw88/rtw8822c.c
@@ -1015,8 +1015,28 @@ static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
                rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
                rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF);
 
-               rtw_write32_mask(rtwdev, REG_RXAGCCTL0, 0x1f0, 0x0);
-               rtw_write32_mask(rtwdev, REG_RXAGCCTL, 0x1f0, 0x0);
+               switch (bw) {
+               case RTW_CHANNEL_WIDTH_20:
+                       rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
+                                        0x5);
+                       rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
+                                        0x5);
+                       rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
+                                        0x6);
+                       rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
+                                        0x6);
+                       break;
+               case RTW_CHANNEL_WIDTH_40:
+                       rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
+                                        0x4);
+                       rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
+                                        0x4);
+                       rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
+                                        0x0);
+                       rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
+                                        0x0);
+                       break;
+               }
                if (channel == 13 || channel == 14)
                        rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969);
                else if (channel == 11 || channel == 12)
@@ -1061,14 +1081,20 @@ static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
                rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22);
                rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
                if (channel >= 36 && channel <= 64) {
-                       rtw_write32_mask(rtwdev, REG_RXAGCCTL0, 0x1f0, 0x1);
-                       rtw_write32_mask(rtwdev, REG_RXAGCCTL, 0x1f0, 0x1);
+                       rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
+                                        0x1);
+                       rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
+                                        0x1);
                } else if (channel >= 100 && channel <= 144) {
-                       rtw_write32_mask(rtwdev, REG_RXAGCCTL0, 0x1f0, 0x2);
-                       rtw_write32_mask(rtwdev, REG_RXAGCCTL, 0x1f0, 0x2);
+                       rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
+                                        0x2);
+                       rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
+                                        0x2);
                } else if (channel >= 149) {
-                       rtw_write32_mask(rtwdev, REG_RXAGCCTL0, 0x1f0, 0x3);
-                       rtw_write32_mask(rtwdev, REG_RXAGCCTL, 0x1f0, 0x3);
+                       rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
+                                        0x3);
+                       rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
+                                        0x3);
                }
 
                if (channel >= 36 && channel <= 51)
@@ -1092,6 +1118,9 @@ static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0);
                rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7);
                rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6);
+               rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
+               rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
+               rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
                break;
        case RTW_CHANNEL_WIDTH_40:
                rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4),
@@ -1100,12 +1129,17 @@ static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
                                 (primary_ch_idx | (primary_ch_idx << 4)));
+               rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1);
+               rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
+               rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
                break;
        case RTW_CHANNEL_WIDTH_80:
                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa);
                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
                                 (primary_ch_idx | (primary_ch_idx << 4)));
+               rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6);
+               rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
                break;
        case RTW_CHANNEL_WIDTH_5:
                rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
@@ -1113,6 +1147,9 @@ static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1);
                rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4);
                rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4);
+               rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
+               rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
+               rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
                break;
        case RTW_CHANNEL_WIDTH_10:
                rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
@@ -1120,6 +1157,9 @@ static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2);
                rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6);
                rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5);
+               rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
+               rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
+               rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
                break;
        }
 }

diff --git a/drivers/net/wireless/realtek/rtw88/rtw8822c.h b/drivers/net/wireless/realtek/rtw88/rtw8822c.h
index d3bd9850baa0b806530ca06a05e385f637d55a3e..ef708ba08ac19e6aa141ae6b411c95678dc6126c 100644 (file)
--- a/drivers/net/wireless/realtek/rtw88/rtw8822c.h
+++ b/drivers/net/wireless/realtek/rtw88/rtw8822c.h
@@ -133,6 +133,8 @@ struct rtw8822c_efuse {
 #define REG_DYMPRITH   0x86c
 #define REG_DYMENTH0   0x870
 #define REG_DYMENTH    0x874
+#define REG_SBD                0x88c
+#define BITS_SUBTUNE           GENMASK(15, 12)
 #define REG_DYMTHMIN   0x8a4
 #define REG_TXBWCTL    0x9b0
 #define REG_TXCLK      0x9b4
@@ -140,12 +142,16 @@ struct rtw8822c_efuse {
 #define REG_MRCM       0xc38
 #define REG_AGCSWSH    0xc44
 #define REG_ANTWTPD    0xc54
+#define REG_PT_CHSMO   0xcbc
+#define BIT_PT_OPT             BIT(21)
 #define REG_ORITXCODE  0x1800
 #define REG_3WIRE      0x180c
 #define BIT_3WIRE_TX_EN                BIT(0)
 #define BIT_3WIRE_RX_EN                BIT(1)
 #define BIT_3WIRE_PI_ON                BIT(28)
 #define REG_RXAGCCTL0  0x18ac
+#define BITS_RXAGC_CCK         GENMASK(15, 12)
+#define BITS_RXAGC_OFDM                GENMASK(8, 4)
 #define REG_CCKSB      0x1a00
 #define REG_RXCCKSEL   0x1a04
 #define REG_BGCTRL     0x1a14
@@ -164,6 +170,8 @@ struct rtw8822c_efuse {
 #define REG_TXF5       0x1aa0
 #define REG_TXF6       0x1aac
 #define REG_TXF7       0x1ab0
+#define REG_CCK_SOURCE 0x1abc
+#define BIT_NBI_EN             BIT(30)
 #define REG_TXANT      0x1c28
 #define REG_ENCCK      0x1c3c
 #define BIT_CCK_BLK_EN         BIT(1)