prompt "Target select"
optional
-config TARGET_VME8349
- bool "Support vme8349"
- select ARCH_MPC8349
-
-config TARGET_CADDY2
- bool "Support caddy2"
- select ARCH_MPC8349
-
config TARGET_MPC8315ERDB
bool "Support MPC8315ERDB"
select ARCH_MPC8315
config FSL_ELBC
bool
-source "board/esd/vme8349/Kconfig"
source "board/freescale/mpc8315erdb/Kconfig"
source "board/freescale/mpc8323erdb/Kconfig"
source "board/freescale/mpc832xemds/Kconfig"
+++ /dev/null
-if TARGET_VME8349
-
-config SYS_BOARD
- default "vme8349"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "vme8349"
-
-endif
-
-if TARGET_CADDY2
-
-config SYS_BOARD
- default "vme8349"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "caddy2"
-
-endif
+++ /dev/null
-VME8349 BOARD
-M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S: Maintained
-F: board/esd/vme8349/
-F: include/configs/vme8349.h
-F: configs/caddy2_defconfig
-F: configs/vme8349_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (c) 2009 esd gmbh hannover germany.
-
-obj-y += vme8349.o caddy.o
-obj-$(CONFIG_PCI) += pci.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
- * Copyright (c) 2009 esd gmbh.
- *
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <console.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <asm/mpc8349_pci.h>
-#include <pci.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-
-#include "caddy.h"
-
-static struct caddy_interface *caddy_interface;
-
-void generate_answer(struct caddy_cmd *cmd, uint32_t status, uint32_t *result)
-{
- struct caddy_answer *answer;
- uint32_t ptr;
-
- answer = &caddy_interface->answer[caddy_interface->answer_in];
- memset((void *)answer, 0, sizeof(struct caddy_answer));
- answer->answer = cmd->cmd;
- answer->issue = cmd->issue;
- answer->status = status;
- memcpy(answer->par, result, 5 * sizeof(result[0]));
- ptr = caddy_interface->answer_in + 1;
- ptr = ptr & (ANSWER_SIZE - 1);
- if (ptr != caddy_interface->answer_out)
- caddy_interface->answer_in = ptr;
-}
-
-int do_caddy(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- unsigned long base_addr;
- uint32_t ptr;
- struct caddy_cmd *caddy_cmd;
- uint32_t result[5];
- uint16_t data16;
- uint8_t data8;
- uint32_t status;
- pci_dev_t dev;
- void *pci_ptr;
-
- if (argc < 2) {
- puts("Missing parameter\n");
- return 1;
- }
-
- base_addr = simple_strtoul(argv[1], NULL, 16);
- caddy_interface = (struct caddy_interface *) base_addr;
-
- memset((void *)caddy_interface, 0, sizeof(struct caddy_interface));
- memcpy((void *)&caddy_interface->magic[0], &CADDY_MAGIC, 16);
-
- while (ctrlc() == 0) {
- if (caddy_interface->cmd_in != caddy_interface->cmd_out) {
- memset(result, 0, 5 * sizeof(result[0]));
- status = 0;
- caddy_cmd = &caddy_interface->cmd[caddy_interface->cmd_out];
- pci_ptr = (void *)CONFIG_SYS_PCI1_IO_PHYS +
- (caddy_cmd->addr & 0x001fffff);
-
- switch (caddy_cmd->cmd) {
- case CADDY_CMD_IO_READ_8:
- result[0] = in_8(pci_ptr);
- break;
-
- case CADDY_CMD_IO_READ_16:
- result[0] = in_be16(pci_ptr);
- break;
-
- case CADDY_CMD_IO_READ_32:
- result[0] = in_be32(pci_ptr);
- break;
-
- case CADDY_CMD_IO_WRITE_8:
- data8 = caddy_cmd->par[0] & 0x000000ff;
- out_8(pci_ptr, data8);
- break;
-
- case CADDY_CMD_IO_WRITE_16:
- data16 = caddy_cmd->par[0] & 0x0000ffff;
- out_be16(pci_ptr, data16);
- break;
-
- case CADDY_CMD_IO_WRITE_32:
- out_be32(pci_ptr, caddy_cmd->par[0]);
- break;
-
- case CADDY_CMD_CONFIG_READ_8:
- dev = PCI_BDF(caddy_cmd->par[0],
- caddy_cmd->par[1],
- caddy_cmd->par[2]);
- status = pci_read_config_byte(dev,
- caddy_cmd->addr,
- &data8);
- result[0] = data8;
- break;
-
- case CADDY_CMD_CONFIG_READ_16:
- dev = PCI_BDF(caddy_cmd->par[0],
- caddy_cmd->par[1],
- caddy_cmd->par[2]);
- status = pci_read_config_word(dev,
- caddy_cmd->addr,
- &data16);
- result[0] = data16;
- break;
-
- case CADDY_CMD_CONFIG_READ_32:
- dev = PCI_BDF(caddy_cmd->par[0],
- caddy_cmd->par[1],
- caddy_cmd->par[2]);
- status = pci_read_config_dword(dev,
- caddy_cmd->addr,
- &result[0]);
- break;
-
- case CADDY_CMD_CONFIG_WRITE_8:
- dev = PCI_BDF(caddy_cmd->par[0],
- caddy_cmd->par[1],
- caddy_cmd->par[2]);
- data8 = caddy_cmd->par[3] & 0x000000ff;
- status = pci_write_config_byte(dev,
- caddy_cmd->addr,
- data8);
- break;
-
- case CADDY_CMD_CONFIG_WRITE_16:
- dev = PCI_BDF(caddy_cmd->par[0],
- caddy_cmd->par[1],
- caddy_cmd->par[2]);
- data16 = caddy_cmd->par[3] & 0x0000ffff;
- status = pci_write_config_word(dev,
- caddy_cmd->addr,
- data16);
- break;
-
- case CADDY_CMD_CONFIG_WRITE_32:
- dev = PCI_BDF(caddy_cmd->par[0],
- caddy_cmd->par[1],
- caddy_cmd->par[2]);
- status = pci_write_config_dword(dev,
- caddy_cmd->addr,
- caddy_cmd->par[3]);
- break;
-
- default:
- status = 0xffffffff;
- break;
- }
-
- generate_answer(caddy_cmd, status, &result[0]);
-
- ptr = caddy_interface->cmd_out + 1;
- ptr = ptr & (CMD_SIZE - 1);
- caddy_interface->cmd_out = ptr;
- }
-
- caddy_interface->heartbeat++;
- }
-
- return 0;
-}
-
-U_BOOT_CMD(
- caddy, 2, 0, do_caddy,
- "Start Caddy server.",
- "Start Caddy server with Data structure a given addr\n"
- );
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
- * Copyright (c) 2009 esd gmbh.
- *
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- */
-
-#ifndef __CADDY_H__
-#define __CADDY_H__
-
-#define CMD_SIZE 1024
-#define ANSWER_SIZE 1024
-#define CADDY_MAGIC "esd vme8349 V1.0"
-
-enum caddy_cmds {
- CADDY_CMD_IO_READ_8,
- CADDY_CMD_IO_READ_16,
- CADDY_CMD_IO_READ_32,
- CADDY_CMD_IO_WRITE_8,
- CADDY_CMD_IO_WRITE_16,
- CADDY_CMD_IO_WRITE_32,
- CADDY_CMD_CONFIG_READ_8,
- CADDY_CMD_CONFIG_READ_16,
- CADDY_CMD_CONFIG_READ_32,
- CADDY_CMD_CONFIG_WRITE_8,
- CADDY_CMD_CONFIG_WRITE_16,
- CADDY_CMD_CONFIG_WRITE_32,
-};
-
-struct caddy_cmd {
- uint32_t cmd;
- uint32_t issue;
- uint32_t addr;
- uint32_t par[5];
-};
-
-struct caddy_answer {
- uint32_t answer;
- uint32_t issue;
- uint32_t status;
- uint32_t par[5];
-};
-
-struct caddy_interface {
- uint8_t magic[16];
- uint32_t cmd_in;
- uint32_t cmd_out;
- uint32_t heartbeat;
- uint32_t reserved1;
- struct caddy_cmd cmd[CMD_SIZE];
- uint32_t answer_in;
- uint32_t answer_out;
- uint32_t reserved2;
- uint32_t reserved3;
- struct caddy_answer answer[CMD_SIZE];
-};
-
-#endif /* of __CADDY_H__ */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * pci.c -- esd VME8349 PCI board support.
- * Copyright (c) 2006 Wind River Systems, Inc.
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- * Copyright (c) 2009 esd gmbh.
- *
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- *
- * Based on MPC8349 PCI support but w/o PIB related code.
- */
-
-#include <init.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include <linux/delay.h>
-#include "vme8349pin.h"
-
-static struct pci_region pci1_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-
-/*
- * pci_init_board()
- *
- * NOTICE: PCI2 is not supported. There is only one
- * physical PCI slot on the board.
- *
- */
-void
-pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- struct pci_region *reg[] = { pci1_regions };
- u8 reg8;
- int monarch = 0;
-
- i2c_set_bus_num(1);
- /* Read the PCI_M66EN jumper setting */
- if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, 1) == 0) ||
- (i2c_read(0x38 , 0, 0, ®8, 1) == 0)) {
- if (reg8 & 0x40) {
- clk->occr = 0xff000000; /* 66 MHz PCI */
- printf("PCI: 66MHz\n");
- } else {
- clk->occr = 0xffff0003; /* 33 MHz PCI */
- printf("PCI: 33MHz\n");
- }
- if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
- monarch = 1;
- } else {
- clk->occr = 0xffff0003; /* 33 MHz PCI */
- printf("PCI: 33MHz (I2C read failed)\n");
- }
- udelay(2000);
-
- /*
- * Assert/deassert VME reset
- */
- clrsetbits_be32(&immr->gpio[1].dat,
- GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
- GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N);
- setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
- GPIO2_TSI_POWERUP_RESET_N |
- GPIO2_VME_RESET_N |
- GPIO2_L_RESET_EN_N);
- clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
- udelay(200);
- setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
- udelay(200);
- setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
- udelay(600000);
- clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
- udelay(2000);
-
- if (monarch == 0) {
- mpc83xx_pci_init(1, reg);
- } else {
- /*
- * Release PCI RST Output signal
- */
- out_be32(&immr->pci_ctrl[0].gcr, 0);
- udelay(2000);
- out_be32(&immr->pci_ctrl[0].gcr, 1);
- }
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * vme8349.c -- esd VME8349 board support
- *
- * Copyright (c) 2008-2009 esd gmbh.
- *
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <init.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <net.h>
-#include <asm/global_data.h>
-#include <asm/mpc8349_pci.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <linux/libfdt.h>
-#endif
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <spd.h>
-#include <spd_sdram.h>
-#include <i2c.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void ddr_enable_ecc(unsigned int dram_size);
-
-int dram_init(void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -ENXIO;
-
- /* DDR SDRAM - Main memory */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
-
- msize = spd_sdram();
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(msize * 1024 * 1024);
-#endif
-
- /* Now check memory size (after ECC is initialized) */
- msize = get_ram_size(0, msize);
-
- /* return total bus SDRAM size(bytes) -- DDR */
- gd->ram_size = msize * 1024 * 1024;
-
- return 0;
-}
-
-int checkboard(void)
-{
-#ifdef CONFIG_TARGET_CADDY2
- puts("Board: esd VME-CADDY/2\n");
-#else
- puts("Board: esd VME-CPU/8349\n");
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_TARGET_CADDY2
-int board_eth_init(struct bd_info *bis)
-{
- return pci_eth_init(bis);
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- ft_cpu_setup(blob, bd);
-
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-
- return 0;
-}
-#endif
-
-int misc_init_r()
-{
- immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
- clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
-
- return 0;
-}
-
-/*
- * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
- * and VME-CADDY/2) have different SDRAM configurations.
- */
-#ifdef CONFIG_TARGET_CADDY2
-#define SMALL_RAM 0xff
-#define LARGE_RAM 0x00
-#else
-#define SMALL_RAM 0x00
-#define LARGE_RAM 0xff
-#endif
-
-#define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM))
-
-static spd_eeprom_t default_spd_eeprom = {
- SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */
- SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */
- SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */
- SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */
- SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */
- SPD_VAL(0x00, 0x00), /* 05 */
- SPD_VAL(0x40, 0x40), /* 06 */
- SPD_VAL(0x00, 0x00), /* 07 */
- SPD_VAL(0x05, 0x05), /* 08 */
- SPD_VAL(0x30, 0x30), /* 09 */
- SPD_VAL(0x45, 0x45), /* 10 */
- SPD_VAL(0x02, 0x02), /* 11 ecc used */
- SPD_VAL(0x82, 0x82), /* 12 */
- SPD_VAL(0x10, 0x10), /* 13 */
- SPD_VAL(0x08, 0x08), /* 14 */
- SPD_VAL(0x00, 0x00), /* 15 */
- SPD_VAL(0x0c, 0x0c), /* 16 */
- SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */
- SPD_VAL(0x38, 0x38), /* 18 */
- SPD_VAL(0x00, 0x00), /* 19 */
- SPD_VAL(0x02, 0x02), /* 20 */
- SPD_VAL(0x00, 0x00), /* 21 */
- SPD_VAL(0x03, 0x03), /* 22 */
- SPD_VAL(0x3d, 0x3d), /* 23 */
- SPD_VAL(0x45, 0x45), /* 24 */
- SPD_VAL(0x50, 0x50), /* 25 */
- SPD_VAL(0x45, 0x45), /* 26 */
- SPD_VAL(0x3c, 0x3c), /* 27 */
- SPD_VAL(0x28, 0x28), /* 28 */
- SPD_VAL(0x3c, 0x3c), /* 29 */
- SPD_VAL(0x2d, 0x2d), /* 30 */
- SPD_VAL(0x20, 0x80), /* 31 */
- SPD_VAL(0x20, 0x20), /* 32 */
- SPD_VAL(0x27, 0x27), /* 33 */
- SPD_VAL(0x10, 0x10), /* 34 */
- SPD_VAL(0x17, 0x17), /* 35 */
- SPD_VAL(0x3c, 0x3c), /* 36 */
- SPD_VAL(0x1e, 0x1e), /* 37 */
- SPD_VAL(0x1e, 0x1e), /* 38 */
- SPD_VAL(0x00, 0x00), /* 39 */
- SPD_VAL(0x00, 0x06), /* 40 */
- SPD_VAL(0x37, 0x37), /* 41 */
- SPD_VAL(0x4b, 0x7f), /* 42 */
- SPD_VAL(0x80, 0x80), /* 43 */
- SPD_VAL(0x18, 0x18), /* 44 */
- SPD_VAL(0x22, 0x22), /* 45 */
- SPD_VAL(0x00, 0x00), /* 46 */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
- SPD_VAL(0x10, 0x10), /* 62 */
- SPD_VAL(0x7e, 0x1d), /* 63 */
- { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
- SPD_VAL(0x00, 0x00), /* 72 */
-#ifdef CONFIG_TARGET_CADDY2
- { "vme-caddy/2 ram " }
-#else
- { "vme-cpu/2 ram " }
-#endif
-};
-
-int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
- int old_bus = i2c_get_bus_num();
- unsigned int l, sum;
- int valid = 0;
-
- i2c_set_bus_num(0);
-
- if (i2c_read(chip, addr, alen, buffer, len) == 0)
- if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
- sum = 0;
- for (l = 0; l < 63; l++)
- sum = (sum + buffer[l]) & 0xff;
- if (sum == buffer[63])
- valid = 1;
- else
- printf("Invalid checksum in EEPROM %02x %02x\n",
- sum, buffer[63]);
- }
-
- if (valid == 0) {
- memcpy(buffer, (void *)&default_spd_eeprom, len);
- sum = 0;
- for (l = 0; l < 63; l++)
- sum = (sum + buffer[l]) & 0xff;
- if (sum != buffer[63])
- printf("Invalid checksum in FLASH %02x %02x\n",
- sum, buffer[63]);
- buffer[63] = sum;
- }
-
- i2c_set_bus_num(old_bus);
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * vme8349pin.h -- esd VME8349 MPC8349 I/O pin definition.
- * Copyright (c) 2009 esd gmbh.
- *
- * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
- */
-
-#ifndef __VME8349PIN_H__
-#define __VME8349PIN_H__
-
-#define GPIO2_V_SCON 0x80000000 /* In: from tsi148 1: is syscon */
-#define GPIO2_VME_RESET_N 0x20000000 /* Out: to tsi148 */
-#define GPIO2_TSI_PLL_RESET_N 0x08000000 /* Out: to tsi148 */
-#define GPIO2_TSI_POWERUP_RESET_N 0x00800000 /* Out: to tsi148 */
-#define GPIO2_L_RESET_EN_N 0x00100000 /* Out: 0:vme can assert cpu lrst*/
-
-#endif /* of ifndef __VME8349PIN_H__ */
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_CADDY2=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_PCI_INT_ARBITER2_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_GMII=y
-CONFIG_TSEC2_MODE_GMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="PCI1_MEM"
-CONFIG_BAT1_BASE=0x80000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="PCI1_MMIO"
-CONFIG_BAT2_BASE=0x90000000
-CONFIG_BAT2_LENGTH_256_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR_PCIIO"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="UNKNOWN"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFFC00000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_4_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF0000000
-CONFIG_LBLAW1_NAME="WINDOW1"
-CONFIG_LBLAW1_LENGTH_256_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFFC00000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_4_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="WINDOW1"
-CONFIG_BR1_OR1_BASE=0xF0000000
-CONFIG_BR1_PORTSIZE_32BIT=y
-CONFIG_OR1_AM_256_KBYTES=y
-CONFIG_OR1_SETA_EXTERNAL=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_TSI148=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFFFC0000
-CONFIG_ENV_ADDR_REDUND=0xFFFE0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_E1000=y
-CONFIG_RTC_RX8025=y
-CONFIG_BAUDRATE=9600
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_SYS_CLK_FREQ=66000000
-CONFIG_MPC83xx=y
-CONFIG_HIGH_BATS=y
-CONFIG_TARGET_VME8349=y
-CONFIG_DDR_MC_CLOCK_MODE_1_1=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_2_1=y
-CONFIG_PCI_HOST_MODE_ENABLE=y
-CONFIG_PCI_64BIT_MODE_ENABLE=y
-CONFIG_PCI_INT_ARBITER1_ENABLE=y
-CONFIG_BOOT_MEMORY_SPACE_LOW=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_GMII=y
-CONFIG_TSEC2_MODE_GMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="SDRAM"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_256_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="PCI1_MEM"
-CONFIG_BAT1_BASE=0x80000000
-CONFIG_BAT1_LENGTH_256_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="PCI1_MMIO"
-CONFIG_BAT2_BASE=0x90000000
-CONFIG_BAT2_LENGTH_256_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT5=y
-CONFIG_BAT5_NAME="IMMR_PCIIO"
-CONFIG_BAT5_BASE=0xE0000000
-CONFIG_BAT5_LENGTH_256_MBYTES=y
-CONFIG_BAT5_ACCESS_RW=y
-CONFIG_BAT5_ICACHE_INHIBITED=y
-CONFIG_BAT5_ICACHE_GUARDED=y
-CONFIG_BAT5_DCACHE_INHIBITED=y
-CONFIG_BAT5_DCACHE_GUARDED=y
-CONFIG_BAT5_USER_MODE_VALID=y
-CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT6=y
-CONFIG_BAT6_NAME="UNKNOWN"
-CONFIG_BAT6_BASE=0xF0000000
-CONFIG_BAT6_LENGTH_256_MBYTES=y
-CONFIG_BAT6_ACCESS_RW=y
-CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT6_USER_MODE_VALID=y
-CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xF8000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_128_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xF0000000
-CONFIG_LBLAW1_NAME="WINDOW1"
-CONFIG_LBLAW1_LENGTH_256_KBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xF8000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_128_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_OR0_EAD_EXTRA=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="WINDOW1"
-CONFIG_BR1_OR1_BASE=0xF0000000
-CONFIG_BR1_PORTSIZE_32BIT=y
-CONFIG_OR1_AM_256_KBYTES=y
-CONFIG_OR1_SETA_EXTERNAL=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_LCRR_CLKDIV_4=y
-CONFIG_PCI_64BIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=6
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_TSI148=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFFFC0000
-CONFIG_ENV_ADDR_REDUND=0xFFFE0000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_TSEC_ENET=y
-CONFIG_RTC_RX8025=y
-CONFIG_BAUDRATE=9600
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
PCI_DEV(dm_pci_get_bdf(dev)));
break;
#endif
-#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
- !defined(CONFIG_TARGET_CADDY2)
+#if defined(CONFIG_ARCH_MPC834X)
case PCI_CLASS_BRIDGE_OTHER:
/*
* The host/PCI bridge 1 seems broken in 8349 - it presents
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * esd vme8349 U-Boot configuration file
- * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
- *
- * (C) Copyright 2006-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * reinhard.arlt@esd-electronics.de
- * Based on the MPC8349EMDS config.
- */
-
-/*
- * vme8349 board configuration file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 Family */
-
-/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
-#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-
-/*
- * DDR Setup
- */
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
-#define CONFIG_SPD_EEPROM
-#define SPD_EEPROM_ADDRESS 0x54
-#define CONFIG_SYS_READ_SPD vme8349_read_spd
-#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
-
-/*
- * 32-bit data path mode.
- *
- * Please note that using this mode for devices with the real density of 64-bit
- * effectively reduces the amount of available memory due to the effect of
- * wrapping around while translating address to row/columns, for example in the
- * 256MB module the upper 128MB get aliased with contents of the lower
- * 128MB); normally this define should be used for devices with real 32-bit
- * data path.
- */
-#undef CONFIG_DDR_32BIT
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
- | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
-#define CONFIG_DDR_2T_TIMING
-#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
- | DDRCDR_ODT \
- | DDRCDR_Q_DRN)
- /* 0x80080001 */
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
-
-
-#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
-
-#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
-
-#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
-
-/* TSEC */
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
-#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
-#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
-
-#if defined(CONFIG_PCI)
-
-
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xFIXME
- #define PCI_ENET0_MEMADDR 0xFIXME
- #define PCI_IDSEL_NUMBER 0xFIXME
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#endif /* CONFIG_PCI */
-
-/*
- * TSEC configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_GMII /* MII PHY management */
-#define CONFIG_TSEC1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_PHY_M88E1111
-#define TSEC1_PHY_ADDR 0x08
-#define TSEC2_PHY_ADDR 0x10
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC0"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-#ifndef CONFIG_SYS_RAMBOOT
-/* Address and size of Redundant Environment Sector */
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_SYS_RTC_BUS_NUM 0x01
-#define CONFIG_SYS_I2C_RTC_ADDR 0x32
-
-/* Pass Ethernet MAC to VxWorks */
-#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH 0
-#define CONFIG_SYS_SICRL SICRL_LDP_A
-
-#define CONFIG_SYS_GPIO1_PRELIM
-#define CONFIG_SYS_GPIO1_DIR 0x00100000
-#define CONFIG_SYS_GPIO1_DAT 0x00100000
-
-#define CONFIG_SYS_GPIO2_PRELIM
-#define CONFIG_SYS_GPIO2_DIR 0x78900000
-#define CONFIG_SYS_GPIO2_DAT 0x70100000
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_HOSTNAME "VME8349"
-#define CONFIG_ROOTPATH "/tftpboot/rootfs"
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=vme8349\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
- "update=protect off fff00000 fff3ffff; " \
- "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
- "upd=run load update\0" \
- "fdtaddr=780000\0" \
- "fdtfile=vme8349.dtb\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#ifndef __ASSEMBLY__
-int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
- unsigned char *buffer, int len);
-#endif
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * esd vme8349 U-Boot configuration file
- * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
- *
- * (C) Copyright 2006-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * reinhard.arlt@esd-electronics.de
- * Based on the MPC8349EMDS config.
- */
-
-/*
- * vme8349 board configuration file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300 1 /* E300 Family */
-
-/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
-#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-
-/*
- * DDR Setup
- */
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
-#define CONFIG_SPD_EEPROM
-#define SPD_EEPROM_ADDRESS 0x54
-#define CONFIG_SYS_READ_SPD vme8349_read_spd
-#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
-
-/*
- * 32-bit data path mode.
- *
- * Please note that using this mode for devices with the real density of 64-bit
- * effectively reduces the amount of available memory due to the effect of
- * wrapping around while translating address to row/columns, for example in the
- * 256MB module the upper 128MB get aliased with contents of the lower
- * 128MB); normally this define should be used for devices with real 32-bit
- * data path.
- */
-#undef CONFIG_DDR_32BIT
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
- | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
-#define CONFIG_DDR_2T_TIMING
-#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
- | DDRCDR_ODT \
- | DDRCDR_Q_DRN)
- /* 0x80080001 */
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
-#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
-
-
-#define CONFIG_SYS_WINDOW1_BASE 0xf0000000
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
-
-#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
-
-#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
-
-/* TSEC */
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
-#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
-#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
-
-#if defined(CONFIG_PCI)
-
-
-#if !defined(CONFIG_PCI_PNP)
- #define PCI_ENET0_IOADDR 0xFIXME
- #define PCI_ENET0_MEMADDR 0xFIXME
- #define PCI_IDSEL_NUMBER 0xFIXME
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-
-#endif /* CONFIG_PCI */
-
-/*
- * TSEC configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_GMII /* MII PHY management */
-#define CONFIG_TSEC1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_PHY_M88E1111
-#define TSEC1_PHY_ADDR 0x08
-#define TSEC2_PHY_ADDR 0x10
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC0"
-
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-#ifndef CONFIG_SYS_RAMBOOT
-/* Address and size of Redundant Environment Sector */
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_SYS_RTC_BUS_NUM 0x01
-#define CONFIG_SYS_I2C_RTC_ADDR 0x32
-
-/* Pass Ethernet MAC to VxWorks */
-#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH 0
-#define CONFIG_SYS_SICRL SICRL_LDP_A
-
-#define CONFIG_SYS_GPIO1_PRELIM
-#define CONFIG_SYS_GPIO1_DIR 0x00100000
-#define CONFIG_SYS_GPIO1_DAT 0x00100000
-
-#define CONFIG_SYS_GPIO2_PRELIM
-#define CONFIG_SYS_GPIO2_DIR 0x78900000
-#define CONFIG_SYS_GPIO2_DAT 0x70100000
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_HOSTNAME "VME8349"
-#define CONFIG_ROOTPATH "/tftpboot/rootfs"
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "hostname=vme8349\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_nfs=run nfsargs addip addtty;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
- "bootm\0" \
- "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
- "update=protect off fff00000 fff3ffff; " \
- "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
- "upd=run load update\0" \
- "fdtaddr=780000\0" \
- "fdtfile=vme8349.dtb\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#ifndef __ASSEMBLY__
-int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
- unsigned char *buffer, int len);
-#endif
-
-#endif /* __CONFIG_H */
projects / uboot.git / commitdiff