feat(ti): set snoop-delayed exclusive handling on A72 cores

Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or by the
core's SCU delaying to check for the corresponding atomic monitor state.

TI SoCs take the second approach. Set the snoop-delayed exclusive handling
bit to inform the core it needs to delay responses to perform this check.

As J784s4 is currently the only SoC with multiple A72 clusters, limit
this delay to only that device.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I875f64e4f53d47a9a0ccbf3415edc565be7f84d9

diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h
index 3fbc465316007015aeab50938cf372a8ce2ea99f..954f7361f94b86b7e13aa98d5866e7ff60d0b909 100644 (file)
--- a/include/lib/cpus/aarch32/cortex_a72.h
+++ b/include/lib/cpus/aarch32/cortex_a72.h
@@ -37,6 +37,7 @@
 #define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA              (ULL(1) << 49)
 #define CORTEX_A72_CPUACTLR_DCC_AS_DCCI                        (ULL(1) << 44)
 #define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH         (ULL(1) << 32)
+#define CORTEX_A72_CPUACTLR_DELAY_EXCLUSIVE_SNOOP      (ULL(1) << 31)
 
 /*******************************************************************************
  * L2 Control register specific definitions.

diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index f592fdcd006e1f6284001db2e7040f00f92ac446..bef9337f91a5012ec5f6efac97ed82bc76824460 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -40,6 +40,7 @@
 #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA                  (ULL(1) << 49)
 #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI                    (ULL(1) << 44)
 #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH             (ULL(1) << 32)
+#define CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP          (ULL(1) << 31)
 
 /*******************************************************************************
  *  L2 Auxiliary Control register specific definitions.

diff --git a/plat/ti/k3/board/j784s4/board.mk b/plat/ti/k3/board/j784s4/board.mk
index c7fcb00160341bee33b4aba319856542448729a6..68ba1b527e64764d87222b357ea3c0be81564fa4 100644 (file)
--- a/plat/ti/k3/board/j784s4/board.mk
+++ b/plat/ti/k3/board/j784s4/board.mk
@@ -21,6 +21,10 @@ $(eval $(call add_define,K3_SEC_PROXY_LITE))
 K3_DATA_RAM_4_LATENCY  :=      1
 $(eval $(call add_define,K3_DATA_RAM_4_LATENCY))
 
+# Delay snoop exclusive handling for J784s4
+K3_EXCLUSIVE_SNOOP_DELAY       :=      1
+$(eval $(call add_define,K3_EXCLUSIVE_SNOOP_DELAY))
+
 # System coherency is managed in hardware
 USE_COHERENT_MEM       :=      1
 

diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S
index da94c16442be1146014b821c40538bd73828d43d..f997b46783bf2ee76dcbbd190d05a709bad21ccc 100644 (file)
--- a/plat/ti/k3/common/k3_helpers.S
+++ b/plat/ti/k3/common/k3_helpers.S
@@ -124,6 +124,13 @@ a72:
        orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN
        msr CORTEX_A72_L2ACTLR_EL1, x0
 
+#if K3_EXCLUSIVE_SNOOP_DELAY
+       mrs     x0, CORTEX_A72_CPUACTLR_EL1
+       /* Set Snoop-delayed exclusive handling */
+       orr     x0, x0, #CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP
+       msr     CORTEX_A72_CPUACTLR_EL1, x0
+#endif
+
        isb
        ret
 endfunc plat_reset_handler