+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Faraday USB 2.0 EHCI Controller
- *
- * (C) Copyright 2010 Faraday Technology
- * Dante Su <dantesu@faraday-tech.com>
- */
-
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <usb.h>
-#include <linux/delay.h>
-#include <usb/fusbh200.h>
-#include <usb/fotg210.h>
-
-#include "ehci.h"
-
-#ifndef CFG_USB_EHCI_BASE_LIST
-#define CFG_USB_EHCI_BASE_LIST { CONFIG_USB_EHCI_BASE }
-#endif
-
-union ehci_faraday_regs {
- struct fusbh200_regs usb;
- struct fotg210_regs otg;
-};
-
-static inline int ehci_is_fotg2xx(union ehci_faraday_regs *regs)
-{
- return !readl(®s->usb.easstr);
-}
-
-void faraday_ehci_set_usbmode(struct ehci_ctrl *ctrl)
-{
- /* nothing needs to be done */
-}
-
-int faraday_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
-{
- int spd, ret = PORTSC_PSPD_HS;
- union ehci_faraday_regs *regs;
-
- ret = (void __iomem *)((ulong)ctrl->hcor - 0x10);
- if (ehci_is_fotg2xx(regs))
- spd = OTGCSR_SPD(readl(®s->otg.otgcsr));
- else
- spd = BMCSR_SPD(readl(®s->usb.bmcsr));
-
- switch (spd) {
- case 0: /* full speed */
- ret = PORTSC_PSPD_FS;
- break;
- case 1: /* low speed */
- ret = PORTSC_PSPD_LS;
- break;
- case 2: /* high speed */
- ret = PORTSC_PSPD_HS;
- break;
- default:
- printf("ehci-faraday: invalid device speed\n");
- break;
- }
-
- return ret;
-}
-
-uint32_t *faraday_ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
-{
- /* Faraday EHCI has one and only one portsc register */
- if (port) {
- /* Printing the message would cause a scan failure! */
- debug("The request port(%d) is not configured\n", port);
- return NULL;
- }
-
- /* Faraday EHCI PORTSC register offset is 0x20 from hcor */
- return (uint32_t *)((uint8_t *)ctrl->hcor + 0x20);
-}
-
-static const struct ehci_ops faraday_ehci_ops = {
- .set_usb_mode = faraday_ehci_set_usbmode,
- .get_port_speed = faraday_ehci_get_port_speed,
- .get_portsc_register = faraday_ehci_get_portsc_register,
-};
-
-/*
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- */
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor)
-{
- struct ehci_hccr *hccr;
- struct ehci_hcor *hcor;
- union ehci_faraday_regs *regs;
- uint32_t base_list[] = CFG_USB_EHCI_BASE_LIST;
-
- if (index < 0 || index >= ARRAY_SIZE(base_list))
- return -1;
- ehci_set_controller_priv(index, NULL, &faraday_ehci_ops);
- regs = (void __iomem *)base_list[index];
- hccr = (struct ehci_hccr *)®s->usb.hccr;
- hcor = (struct ehci_hcor *)®s->usb.hcor;
-
- if (ehci_is_fotg2xx(regs)) {
- /* A-device bus reset */
- /* ... Power off A-device */
- setbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSDROP);
- /* ... Drop vbus and bus traffic */
- clrbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSREQ);
- mdelay(1);
- /* ... Power on A-device */
- clrbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSDROP);
- /* ... Drive vbus and bus traffic */
- setbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSREQ);
- mdelay(1);
- /* Disable OTG & DEV interrupts, triggered at level-high */
- writel(IMR_IRQLH | IMR_OTG | IMR_DEV, ®s->otg.imr);
- /* Clear all interrupt status */
- writel(ISR_HOST | ISR_OTG | ISR_DEV, ®s->otg.isr);
- } else {
- /* Interrupt=level-high */
- setbits_le32(®s->usb.bmcsr, BMCSR_IRQLH);
- /* VBUS on */
- clrbits_le32(®s->usb.bmcsr, BMCSR_VBUS_OFF);
- /* Disable all interrupts */
- writel(0x00, ®s->usb.bmier);
- writel(0x1f, ®s->usb.bmisr);
- }
-
- *ret_hccr = hccr;
- *ret_hcor = hcor;
-
- return 0;
-}
-
-/*
- * Destroy the appropriate control structures corresponding
- * the the EHCI host controller.
- */
-int ehci_hcd_stop(int index)
-{
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Faraday USB 2.0 EHCI Controller
- *
- * (C) Copyright 2010 Faraday Technology
- * Dante Su <dantesu@faraday-tech.com>
- */
-
-#ifndef _FUSBH200_H
-#define _FUSBH200_H
-
-struct fusbh200_regs {
- struct {
- uint32_t data[4];
- } hccr; /* 0x00 - 0x0f: hccr */
- struct {
- uint32_t data[9];
- } hcor; /* 0x10 - 0x33: hcor */
- uint32_t easstr;/* 0x34: EOF&Async. Sched. Sleep Timer Register */
- uint32_t rsvd[2];
- uint32_t bmcsr; /* 0x40: Bus Monitor Control Status Register */
- uint32_t bmisr; /* 0x44: Bus Monitor Interrupt Status Register */
- uint32_t bmier; /* 0x48: Bus Monitor Interrupt Enable Register */
-};
-
-/* EOF & Async. Schedule Sleep Timer Register */
-#define EASSTR_RUNNING (1 << 6) /* Put transceiver in running/resume mode */
-#define EASSTR_SUSPEND (0 << 6) /* Put transceiver in suspend mode */
-#define EASSTR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */
-#define EASSTR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */
-#define EASSTR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */
-
-/* Bus Monitor Control Status Register */
-#define BMCSR_SPD_HIGH (2 << 9) /* Speed of the attached device */
-#define BMCSR_SPD_LOW (1 << 9)
-#define BMCSR_SPD_FULL (0 << 9)
-#define BMCSR_SPD_MASK (3 << 9)
-#define BMCSR_SPD_SHIFT 9
-#define BMCSR_SPD(x) ((x >> 9) & 0x03)
-#define BMCSR_VBUS (1 << 8) /* VBUS Valid */
-#define BMCSR_VBUS_OFF (1 << 4) /* VBUS Off */
-#define BMCSR_VBUS_ON (0 << 4) /* VBUS On */
-#define BMCSR_IRQLH (1 << 3) /* IRQ triggered at level-high */
-#define BMCSR_IRQLL (0 << 3) /* IRQ triggered at level-low */
-#define BMCSR_HALFSPD (1 << 2) /* Half speed mode for FPGA test */
-#define BMCSR_HFT_LONG (1 << 1) /* HDISCON noise filter = 270 us*/
-#define BMCSR_HFT (0 << 1) /* HDISCON noise filter = 135 us*/
-#define BMCSR_VFT_LONG (1 << 1) /* VBUS noise filter = 472 us*/
-#define BMCSR_VFT (0 << 1) /* VBUS noise filter = 135 us*/
-
-/* Bus Monitor Interrupt Status Register */
-/* Bus Monitor Interrupt Enable Register */
-#define BMISR_DMAERR (1 << 4) /* DMA error */
-#define BMISR_DMA (1 << 3) /* DMA complete */
-#define BMISR_DEVRM (1 << 2) /* device removed */
-#define BMISR_OVD (1 << 1) /* over-current detected */
-#define BMISR_VBUSERR (1 << 0) /* VBUS error */
-
-#endif