drm/amd/amdgpu: Recovery vcn instance iterate.

The previous logic is recording the amount of valid vcn instances
to use them on SRIOV, it is a hard task due to the vcn accessment is
based on the index of the vcn instance.

Check if the vcn instance enabled before do instance init.

Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 2f017560948ebe7242977e33bd6a156d309faf4e..3d18aab88b4e24edcb30d0f2feb8dcd8ec8cce7b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -90,9 +90,7 @@ static int vcn_v3_0_early_init(void *handle)
        int i;
 
        if (amdgpu_sriov_vf(adev)) {
-               for (i = 0; i < VCN_INSTANCES_SIENNA_CICHLID; i++)
-                       if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i))
-                               adev->vcn.num_vcn_inst++;
+               adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
                adev->vcn.harvest_config = 0;
                adev->vcn.num_enc_rings = 1;
 
@@ -153,8 +151,7 @@ static int vcn_v3_0_sw_init(void *handle)
                adev->firmware.fw_size +=
                        ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 
-               if ((adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) ||
-                   (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)) {
+               if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) {
                        adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1;
                        adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;
                        adev->firmware.fw_size +=
@@ -328,18 +325,28 @@ static int vcn_v3_0_hw_init(void *handle)
                                continue;
 
                        ring = &adev->vcn.inst[i].ring_dec;
-                       ring->wptr = 0;
-                       ring->wptr_old = 0;
-                       vcn_v3_0_dec_ring_set_wptr(ring);
-                       ring->sched.ready = true;
-
-                       for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
-                               ring = &adev->vcn.inst[i].ring_enc[j];
+                       if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i)) {
+                               ring->sched.ready = false;
+                               dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name);
+                       } else {
                                ring->wptr = 0;
                                ring->wptr_old = 0;
-                               vcn_v3_0_enc_ring_set_wptr(ring);
+                               vcn_v3_0_dec_ring_set_wptr(ring);
                                ring->sched.ready = true;
                        }
+
+                       for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+                               ring = &adev->vcn.inst[i].ring_enc[j];
+                               if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) {
+                                       ring->sched.ready = false;
+                                       dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name);
+                               } else {
+                                       ring->wptr = 0;
+                                       ring->wptr_old = 0;
+                                       vcn_v3_0_enc_ring_set_wptr(ring);
+                                       ring->sched.ready = true;
+                               }
+                       }
                }
        } else {
                for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {