[POWERPC] 85xx: mpc85xx_mds - reset UCC ethernet properly

Apart from that the current code doesn't compile it's also
meaningless with regard to the MPC8568E-MDS' BCSR.

This patch used to reset UCCs properly.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 57e840a1c027599bb8a13a68b17d3bb83cc93cc7..6913e99c127996ee2d95631f08973c50b3528b47 100644 (file)
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -113,18 +113,22 @@ static void __init mpc85xx_mds_setup_arch(void)
        }
 
        if (bcsr_regs) {
-               u8 bcsr_phy;
-
-               /* Reset the Ethernet PHY */
-               bcsr_phy = in_be8(&bcsr_regs[9]);
-               bcsr_phy &= ~0x20;
-               out_be8(&bcsr_regs[9], bcsr_phy);
-
-               udelay(1000);
-
-               bcsr_phy = in_be8(&bcsr_regs[9]);
-               bcsr_phy |= 0x20;
-               out_be8(&bcsr_regs[9], bcsr_phy);
+#define BCSR_UCC1_GETH_EN      (0x1 << 7)
+#define BCSR_UCC2_GETH_EN      (0x1 << 7)
+#define BCSR_UCC1_MODE_MSK     (0x3 << 4)
+#define BCSR_UCC2_MODE_MSK     (0x3 << 0)
+
+               /* Turn off UCC1 & UCC2 */
+               clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
+               clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+
+               /* Mode is RGMII, all bits clear */
+               clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
+                                        BCSR_UCC2_MODE_MSK);
+
+               /* Turn UCC1 & UCC2 on */
+               setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
+               setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
 
                iounmap(bcsr_regs);
        }