drm/i915/dg2: Enable 5th port

DG2 supports a 5th display output which the hardware refers to as "TC1,"
even though it isn't a Type-C output.  This behaves similarly to the TC1
on past platforms with just a couple minor differences:

 * DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
   ICP/TGP/ADP.
 * DG2 doesn't need the hpd inversion setting that we had to use on DG1

v2:
  intel_ddi_init(dev_priv, PORT_TC1); [Matt]

Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220218010328.183423-3-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f60eb39bfdff331399ed3e44031a0ca2d8801089..37bbb0333d9cca25a0df540c4ca1878b2397d045 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8757,6 +8757,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
                intel_ddi_init(dev_priv, PORT_B);
                intel_ddi_init(dev_priv, PORT_C);
                intel_ddi_init(dev_priv, PORT_D_XELPD);
+               intel_ddi_init(dev_priv, PORT_TC1);
        } else if (IS_ALDERLAKE_P(dev_priv)) {
                intel_ddi_init(dev_priv, PORT_A);
                intel_ddi_init(dev_priv, PORT_B);

diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 6ce8c10fe975cfcb6f9a75a2d55a7194da33f637..2fad03250661a9350e5111b050daefe1489b6b37 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -98,11 +98,21 @@ static const struct gmbus_pin gmbus_pins_dg1[] = {
        [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
 };
 
+static const struct gmbus_pin gmbus_pins_dg2[] = {
+       [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+       [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+       [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+       [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+       [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+};
+
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
                                             unsigned int pin)
 {
-       if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+       if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
+               return &gmbus_pins_dg2[pin];
+       else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
                return &gmbus_pins_dg1[pin];
        else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
                return &gmbus_pins_icp[pin];
@@ -123,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 {
        unsigned int size;
 
-       if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+       if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
+               size = ARRAY_SIZE(gmbus_pins_dg2);
+       else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
                size = ARRAY_SIZE(gmbus_pins_dg1);
        else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
                size = ARRAY_SIZE(gmbus_pins_icp);

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index fdd568ba4a161c7e77f687c6d477f9e4d70ba06d..4d81063b128cc0f22866e7b2d5d3ead10a10e9ea 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -179,6 +179,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
        [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
        [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
        [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
+       [HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
 };
 
 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
@@ -4424,7 +4425,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
                if (I915_HAS_HOTPLUG(dev_priv))
                        dev_priv->hotplug_funcs = &i915_hpd_funcs;
        } else {
-               if (HAS_PCH_DG1(dev_priv))
+               if (HAS_PCH_DG2(dev_priv))
+                       dev_priv->hotplug_funcs = &icp_hpd_funcs;
+               else if (HAS_PCH_DG1(dev_priv))
                        dev_priv->hotplug_funcs = &dg1_hpd_funcs;
                else if (DISPLAY_VER(dev_priv) >= 11)
                        dev_priv->hotplug_funcs = &gen11_hpd_funcs;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c6095c33a3317b63b2a3c16394a89779cfbe6155..580763515b16fa65c921ad13fccf977fbacbe815 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6059,6 +6059,7 @@
 /* south display engine interrupt: ICP/TGP */
 #define SDE_GMBUS_ICP                  (1 << 23)
 #define SDE_TC_HOTPLUG_ICP(hpd_pin)    REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
+#define SDE_TC_HOTPLUG_DG2(hpd_pin)    REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
 #define SDE_DDI_HOTPLUG_ICP(hpd_pin)   REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
 #define SDE_DDI_HOTPLUG_MASK_ICP       (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
                                         SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \