drm/amdgpu/mes: only invalid/prime icache when finish loading both pipe MES FWs.

invalid/prime icahce operation takes effect both pipes cuconrrently,
therefore CP_MES_IC_BASE_LO/HI and CP_MES_MDBASE_LO/HI both have to be
set before prime icache. Otherwise MES hardware gets garbage data in
above regsters and causes page fault

[  470.873200] amdgpu 0000:33:00.0: amdgpu: [gfxhub] page fault (src_id:0 ring:217 vmid:0 pasid:0, for process  pid 0 thread  pid 0)
[  470.873222] amdgpu 0000:33:00.0: amdgpu:   in page starting at address 0x000092cb89b00000 from client 10
[  470.873234] amdgpu 0000:33:00.0: amdgpu: GCVM_L2_PROTECTION_FAULT_STATUS:0x00000BB3
[  470.873242] amdgpu 0000:33:00.0: amdgpu:      Faulty UTCL2 client ID: CPC (0x5)
[  470.873247] amdgpu 0000:33:00.0: amdgpu:      MORE_FAULTS: 0x1
[  470.873251] amdgpu 0000:33:00.0: amdgpu:      WALKER_ERROR: 0x1
[  470.873256] amdgpu 0000:33:00.0: amdgpu:      PERMISSION_FAULTS: 0xb
[  470.873260] amdgpu 0000:33:00.0: amdgpu:      MAPPING_ERROR: 0x1
[  470.873264] amdgpu 0000:33:00.0: amdgpu:      RW: 0x0

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index fcf51947bb186f8575fd608342b4fa6d7d5485e9..7eee004cf3ce39ef9f6d3741ecf4ec90657961c6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -541,7 +541,7 @@ static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
 
 /* This function is for backdoor MES firmware */
 static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
-                                   enum admgpu_mes_pipe pipe)
+                                   enum admgpu_mes_pipe pipe, bool prime_icache)
 {
        int r;
        uint32_t data;
@@ -593,16 +593,18 @@ static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
        /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */
        WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF);
 
-       /* invalidate ICACHE */
-       data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
-       data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
-       data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
-       WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
-
-       /* prime the ICACHE. */
-       data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
-       data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
-       WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
+       if (prime_icache) {
+               /* invalidate ICACHE */
+               data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
+               data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
+               data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
+               WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
+
+               /* prime the ICACHE. */
+               data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
+               data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
+               WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
+       }
 
        soc21_grbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
@@ -1044,17 +1046,19 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
        int r = 0;
 
        if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
-               r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE);
+
+               r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
                if (r) {
-                       DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
+                       DRM_ERROR("failed to load MES fw, r=%d\n", r);
                        return r;
                }
 
-               r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE);
+               r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
                if (r) {
-                       DRM_ERROR("failed to load MES fw, r=%d\n", r);
+                       DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
                        return r;
                }
+
        }
 
        mes_v11_0_enable(adev, true);
@@ -1086,7 +1090,7 @@ static int mes_v11_0_hw_init(void *handle)
        if (!adev->enable_mes_kiq) {
                if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
                        r = mes_v11_0_load_microcode(adev,
-                                            AMDGPU_MES_SCHED_PIPE);
+                                            AMDGPU_MES_SCHED_PIPE, true);
                        if (r) {
                                DRM_ERROR("failed to MES fw, r=%d\n", r);
                                return r;