help
Debug Event Register (37-47)
-source "board/cssi/MCR3000/Kconfig"
+source "board/cssi/mcr3000/Kconfig"
endmenu
M: Christophe Leroy <christophe.leroy@csgroup.eu>
S: Maintained
F: board/cssi/
-F: include/configs/MCR3000.h
+F: include/configs/mcr3000.h
F: configs/MCR3000_defconfig
+++ /dev/null
-if TARGET_MCR3000
-
-config SYS_BOARD
- default "MCR3000"
-
-config SYS_VENDOR
- default "cssi"
-
-config SYS_CONFIG_NAME
- default "MCR3000"
-
-config TEXT_BASE
- default 0x04000000
-
-endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2010-2017 CS Systemes d'Information
- * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
- * Christophe Leroy <christophe.leroy@c-s.fr>
- *
- * Board specific routines for the MCR3000 board
- */
-
-#include <common.h>
-#include <env.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <mpc8xx.h>
-#include <fdt_support.h>
-#include <serial.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <dm/uclass.h>
-#include <wdt.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define SDRAM_MAX_SIZE (32 * 1024 * 1024)
-
-static const uint cs1_dram_table_66[] = {
- /* DRAM - single read. (offset 0 in upm RAM) */
- 0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
- 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* DRAM - burst read. (offset 8 in upm RAM) */
- 0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
- 0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* DRAM - single write. (offset 18 in upm RAM) */
- 0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
- 0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* DRAM - burst write. (offset 20 in upm RAM) */
- 0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
- 0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404,
- 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-
- /* refresh (offset 30 in upm RAM) */
- 0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
- 0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
-
- /* init */
- 0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
-
- /* exception. (offset 3c in upm RAM) */
- 0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-};
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- const char *sync = "receive";
-
- ft_cpu_setup(blob, bd);
-
- /* BRG */
- do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
- bd->bi_busfreq, 1);
-
- /* MAC addr */
- fdt_fixup_ethernet(blob);
-
- /* Bus Frequency for CPM */
- do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
-
- /* E1 interface - Set data rate */
- do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
-
- /* E1 interface - Set channel phase to 0 */
- do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
-
- /* E1 interface - rising edge sync pulse transmit */
- do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
- sync, strlen(sync), 1);
-
- return 0;
-}
-
-int checkboard(void)
-{
- serial_puts("BOARD: MCR3000 CSSI\n");
-
- return 0;
-}
-
-int dram_init(void)
-{
- immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
- memctl8xx_t __iomem *memctl = &immap->im_memctl;
-
- printf("UPMA init for SDRAM (CAS latency 2), ");
- printf("init address 0x%08x, size ", (int)dram_init);
- /* Configure UPMA for cs1 */
- upmconfig(UPMA, (uint *)cs1_dram_table_66,
- sizeof(cs1_dram_table_66) / sizeof(uint));
- udelay(10);
- out_be16(&memctl->memc_mptpr, 0x0200);
- out_be32(&memctl->memc_mamr, 0x14904000);
- udelay(10);
- out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
- out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
- udelay(10);
- out_be32(&memctl->memc_mcr, 0x80002830);
- out_be32(&memctl->memc_mar, 0x00000088);
- out_be32(&memctl->memc_mcr, 0x80002038);
- udelay(200);
-
- gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
- SDRAM_MAX_SIZE);
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
- iop8xx_t __iomem *iop = &immr->im_ioport;
-
- /* Set port C13 as GPIO (BTN_ACQ_AL) */
- clrbits_be16(&iop->iop_pcpar, 0x4);
- clrbits_be16(&iop->iop_pcdir, 0x4);
-
- /* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
- if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
- env_set("bootdelay", "60");
-
- return 0;
-}
-
-int board_early_init_f(void)
-{
- immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
-
- /*
- * Erase FPGA(s) for reboot
- */
- clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */
- setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */
- udelay(1); /* Wait more than 300ns */
- setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- struct udevice *watchdog_dev = NULL;
-
- if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
- puts("Cannot find watchdog!\n");
- } else {
- puts("Enabling watchdog.\n");
- wdt_start(watchdog_dev, 0xffff, 0);
- }
-
- return 0;
-}
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2010-2017 CS Systemes d'Information
-# Christophe Leroy <christophe.leroy@c-s.fr>
-#
-
-obj-y += MCR3000.o
-obj-$(CONFIG_CMD_NAND) += nand.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2010-2017 CS Systemes d'Information
- * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
- * Christophe Leroy <christophe.leroy@c-s.fr>
- */
-
-#include <config.h>
-#include <common.h>
-#include <nand.h>
-#include <linux/mtd/rawnand.h>
-#include <asm/io.h>
-
-#define BIT_CLE ((unsigned short)0x0800)
-#define BIT_ALE ((unsigned short)0x0400)
-#define BIT_NCE ((unsigned short)0x1000)
-
-static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd_to_nand(mtdinfo);
- immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
- unsigned short pddat = 0;
-
- /* The hardware control change */
- if (ctrl & NAND_CTRL_CHANGE) {
- pddat = in_be16(&immr->im_ioport.iop_pddat);
-
- /* Clearing ALE and CLE */
- pddat &= ~(BIT_CLE | BIT_ALE);
-
- /* Driving NCE pin */
- if (ctrl & NAND_NCE)
- pddat &= ~BIT_NCE;
- else
- pddat |= BIT_NCE;
-
- /* Driving CLE and ALE pin */
- if (ctrl & NAND_CLE)
- pddat |= BIT_CLE;
- if (ctrl & NAND_ALE)
- pddat |= BIT_ALE;
-
- out_be16(&immr->im_ioport.iop_pddat, pddat);
- }
-
- /* Writing the command */
- if (cmd != NAND_CMD_NONE)
- out_8(this->IO_ADDR_W, cmd);
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
-
- /* Set GPIO Port */
- setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00);
- clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00);
- clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000);
-
- nand->chip_delay = 60;
- nand->ecc.mode = NAND_ECC_SOFT;
- nand->cmd_ctrl = nand_hwcontrol;
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010-2017 CS Systemes d'Information
- * Christophe Leroy <christophe.leroy@c-s.fr>
- *
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified by Yuli Barcohen <yuli@arabellasw.com>
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- arch/powerpc/lib/built-in.o (.text*)
- drivers/net/built-in.o (.text*)
-
- . = DEFINED(env_offset) ? env_offset : .;
- env/embedded.o (.text.environment)
-
- *(.text)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- __u_boot_list : {
- KEEP(*(SORT(__u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- /*
- * _end - This is end of u-boot.bin image.
- * dtb will be appended here to make u-boot-dtb.bin
- */
- _end = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
-ENTRY(_start)
--- /dev/null
+if TARGET_MCR3000
+
+config SYS_BOARD
+ default "mcr3000"
+
+config SYS_VENDOR
+ default "cssi"
+
+config SYS_CONFIG_NAME
+ default "mcr3000"
+
+config TEXT_BASE
+ default 0x04000000
+
+endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2010-2017 CS Systemes d'Information
+# Christophe Leroy <christophe.leroy@c-s.fr>
+#
+
+obj-y += mcr3000.o
+obj-$(CONFIG_CMD_NAND) += nand.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ *
+ * Board specific routines for the MCR3000 board
+ */
+
+#include <common.h>
+#include <env.h>
+#include <hwconfig.h>
+#include <init.h>
+#include <mpc8xx.h>
+#include <fdt_support.h>
+#include <serial.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <dm/uclass.h>
+#include <wdt.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SDRAM_MAX_SIZE (32 * 1024 * 1024)
+
+static const uint cs1_dram_table_66[] = {
+ /* DRAM - single read. (offset 0 in upm RAM) */
+ 0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
+ 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* DRAM - burst read. (offset 8 in upm RAM) */
+ 0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
+ 0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* DRAM - single write. (offset 18 in upm RAM) */
+ 0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
+ 0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* DRAM - burst write. (offset 20 in upm RAM) */
+ 0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
+ 0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404,
+ 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+ /* refresh (offset 30 in upm RAM) */
+ 0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
+ 0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
+
+ /* init */
+ 0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
+
+ /* exception. (offset 3c in upm RAM) */
+ 0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+};
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ const char *sync = "receive";
+
+ ft_cpu_setup(blob, bd);
+
+ /* BRG */
+ do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
+ bd->bi_busfreq, 1);
+
+ /* MAC addr */
+ fdt_fixup_ethernet(blob);
+
+ /* Bus Frequency for CPM */
+ do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
+
+ /* E1 interface - Set data rate */
+ do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
+
+ /* E1 interface - Set channel phase to 0 */
+ do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
+
+ /* E1 interface - rising edge sync pulse transmit */
+ do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
+ sync, strlen(sync), 1);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ serial_puts("BOARD: MCR3000 CSSI\n");
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ memctl8xx_t __iomem *memctl = &immap->im_memctl;
+
+ printf("UPMA init for SDRAM (CAS latency 2), ");
+ printf("init address 0x%08x, size ", (int)dram_init);
+ /* Configure UPMA for cs1 */
+ upmconfig(UPMA, (uint *)cs1_dram_table_66,
+ sizeof(cs1_dram_table_66) / sizeof(uint));
+ udelay(10);
+ out_be16(&memctl->memc_mptpr, 0x0200);
+ out_be32(&memctl->memc_mamr, 0x14904000);
+ udelay(10);
+ out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
+ out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
+ udelay(10);
+ out_be32(&memctl->memc_mcr, 0x80002830);
+ out_be32(&memctl->memc_mar, 0x00000088);
+ out_be32(&memctl->memc_mcr, 0x80002038);
+ udelay(200);
+
+ gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
+ SDRAM_MAX_SIZE);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ iop8xx_t __iomem *iop = &immr->im_ioport;
+
+ /* Set port C13 as GPIO (BTN_ACQ_AL) */
+ clrbits_be16(&iop->iop_pcpar, 0x4);
+ clrbits_be16(&iop->iop_pcdir, 0x4);
+
+ /* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
+ if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
+ env_set("bootdelay", "60");
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ /*
+ * Erase FPGA(s) for reboot
+ */
+ clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */
+ setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */
+ udelay(1); /* Wait more than 300ns */
+ setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ struct udevice *watchdog_dev = NULL;
+
+ if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
+ puts("Cannot find watchdog!\n");
+ } else {
+ puts("Enabling watchdog.\n");
+ wdt_start(watchdog_dev, 0xffff, 0);
+ }
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ */
+
+#include <config.h>
+#include <common.h>
+#include <nand.h>
+#include <linux/mtd/rawnand.h>
+#include <asm/io.h>
+
+#define BIT_CLE ((unsigned short)0x0800)
+#define BIT_ALE ((unsigned short)0x0400)
+#define BIT_NCE ((unsigned short)0x1000)
+
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd_to_nand(mtdinfo);
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+ unsigned short pddat = 0;
+
+ /* The hardware control change */
+ if (ctrl & NAND_CTRL_CHANGE) {
+ pddat = in_be16(&immr->im_ioport.iop_pddat);
+
+ /* Clearing ALE and CLE */
+ pddat &= ~(BIT_CLE | BIT_ALE);
+
+ /* Driving NCE pin */
+ if (ctrl & NAND_NCE)
+ pddat &= ~BIT_NCE;
+ else
+ pddat |= BIT_NCE;
+
+ /* Driving CLE and ALE pin */
+ if (ctrl & NAND_CLE)
+ pddat |= BIT_CLE;
+ if (ctrl & NAND_ALE)
+ pddat |= BIT_ALE;
+
+ out_be16(&immr->im_ioport.iop_pddat, pddat);
+ }
+
+ /* Writing the command */
+ if (cmd != NAND_CMD_NONE)
+ out_8(this->IO_ADDR_W, cmd);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+ /* Set GPIO Port */
+ setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00);
+ clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00);
+ clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000);
+
+ nand->chip_delay = 60;
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = nand_hwcontrol;
+
+ return 0;
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ *
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .text :
+ {
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ arch/powerpc/lib/built-in.o (.text*)
+ drivers/net/built-in.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ env/embedded.o (.text.environment)
+
+ *(.text)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ __u_boot_list : {
+ KEEP(*(SORT(__u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ /*
+ * _end - This is end of u-boot.bin image.
+ * dtb will be appended here to make u-boot-dtb.bin
+ */
+ _end = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
+ENTRY(_start)
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010-2017 CS Systemes d'Information
- * Christophe Leroy <christophe.leroy@c-s.fr>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-
-#define CFG_EXTRA_ENV_SETTINGS \
- "sdram_type=SDRAM\0" \
- "flash_type=AM29LV160DB\0" \
- "loadaddr=0x400000\0" \
- "filename=uImage.lzma\0" \
- "nfsroot=/opt/ofs\0" \
- "dhcp_ip=ip=:::::eth0:dhcp\0" \
- "console_args=console=ttyCPM0,115200N8\0" \
- "flashboot=setenv bootargs " \
- "${console_args} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
- "mcr3k:eth0:off;" \
- "${ofl_args}; " \
- "bootm 0x04060000 - 0x04050000\0" \
- "tftpboot=setenv bootargs " \
- "${console_args} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
- "mcr3k:eth0:off " \
- "${ofl_args}; " \
- "tftp ${loadaddr} ${filename};" \
- "tftp 0xf00000 mcr3000.dtb;" \
- "bootm ${loadaddr} - 0xf00000\0" \
- "netboot=dhcp ${loadaddr} ${filename};" \
- "tftp 0xf00000 mcr3000.dtb;" \
- "setenv bootargs " \
- "root=/dev/nfs rw " \
- "${console_args} " \
- "${dhcp_ip};" \
- "bootm ${loadaddr} - 0xf00000\0" \
- "nfsboot=setenv bootargs " \
- "root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} " \
- "${console_args} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
- "mcr3k:eth0:off;" \
- "bootm 0x04060000 - 0x04050000\0" \
- "dhcpboot=dhcp ${loadaddr} ${filename};" \
- "tftp 0xf00000 mcr3000.dtb;" \
- "setenv bootargs " \
- "${console_args} " \
- "${dhcp_ip} " \
- "${ofl_args}; " \
- "bootm ${loadaddr} - 0xf00000\0"
-
-/* Miscellaneous configurable options */
-
-/* Definitions for initial stack pointer and data area (in DPRAM) */
-#define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
-#define CFG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
-
-/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */
-#define CFG_SYS_SDRAM_BASE 0x00000000
-
-/* FLASH organization */
-#define CFG_SYS_FLASH_BASE CONFIG_TEXT_BASE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CFG_SYS_BOOTMAPSZ (8 << 20)
-
-/* Environment Configuration */
-
-/* environment is in FLASH */
-
-/* Ethernet configuration part */
-
-/* NAND configuration part */
-#define CFG_SYS_NAND_BASE 0x0C000000
-
-#endif /* __CONFIG_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ "sdram_type=SDRAM\0" \
+ "flash_type=AM29LV160DB\0" \
+ "loadaddr=0x400000\0" \
+ "filename=uImage.lzma\0" \
+ "nfsroot=/opt/ofs\0" \
+ "dhcp_ip=ip=:::::eth0:dhcp\0" \
+ "console_args=console=ttyCPM0,115200N8\0" \
+ "flashboot=setenv bootargs " \
+ "${console_args} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
+ "mcr3k:eth0:off;" \
+ "${ofl_args}; " \
+ "bootm 0x04060000 - 0x04050000\0" \
+ "tftpboot=setenv bootargs " \
+ "${console_args} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
+ "mcr3k:eth0:off " \
+ "${ofl_args}; " \
+ "tftp ${loadaddr} ${filename};" \
+ "tftp 0xf00000 mcr3000.dtb;" \
+ "bootm ${loadaddr} - 0xf00000\0" \
+ "netboot=dhcp ${loadaddr} ${filename};" \
+ "tftp 0xf00000 mcr3000.dtb;" \
+ "setenv bootargs " \
+ "root=/dev/nfs rw " \
+ "${console_args} " \
+ "${dhcp_ip};" \
+ "bootm ${loadaddr} - 0xf00000\0" \
+ "nfsboot=setenv bootargs " \
+ "root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} " \
+ "${console_args} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
+ "mcr3k:eth0:off;" \
+ "bootm 0x04060000 - 0x04050000\0" \
+ "dhcpboot=dhcp ${loadaddr} ${filename};" \
+ "tftp 0xf00000 mcr3000.dtb;" \
+ "setenv bootargs " \
+ "${console_args} " \
+ "${dhcp_ip} " \
+ "${ofl_args}; " \
+ "bootm ${loadaddr} - 0xf00000\0"
+
+/* Miscellaneous configurable options */
+
+/* Definitions for initial stack pointer and data area (in DPRAM) */
+#define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
+#define CFG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
+
+/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */
+#define CFG_SYS_SDRAM_BASE 0x00000000
+
+/* FLASH organization */
+#define CFG_SYS_FLASH_BASE CONFIG_TEXT_BASE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_SYS_BOOTMAPSZ (8 << 20)
+
+/* Environment Configuration */
+
+/* environment is in FLASH */
+
+/* Ethernet configuration part */
+
+/* NAND configuration part */
+#define CFG_SYS_NAND_BASE 0x0C000000
+
+#endif /* __CONFIG_H */
projects / uboot.git / commitdiff