drm/i915/icl: Add support to read out the TBT PLL HW state

Add support to read out the TBT PLL HW state.

Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190628143635.22066-2-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c97c0a9f62088c03beab380a4a39818817ecabc6..d65a580fe52774137d7fbbc982cf3228e93a2e73 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9928,13 +9928,20 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
        enum intel_dpll_id id;
        u32 temp;
 
-       /* TODO: TBT pll not implemented. */
        if (intel_port_is_combophy(dev_priv, port)) {
                temp = I915_READ(DPCLKA_CFGCR0_ICL) &
                       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
                id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
        } else if (intel_port_is_tc(dev_priv, port)) {
-               id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, port));
+               u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
+
+               if (clk_sel == DDI_CLK_SEL_MG) {
+                       id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
+                                                                   port));
+               } else {
+                       WARN_ON(clk_sel < DDI_CLK_SEL_TBT_162);
+                       id = DPLL_ID_ICL_TBTPLL;
+               }
        } else {
                WARN(1, "Invalid port %x\n", port);
                return;