--- /dev/null
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* TF-A system header */
+#include <common/debug.h>
+
+/* Vendor header */
+#include "apusys.h"
+#include "apusys_power.h"
+#include <lib/mtk_init/mtk_init.h>
+
+int apusys_init(void)
+{
+ apusys_power_init();
+ return 0;
+}
+MTK_PLAT_SETUP_1_INIT(apusys_init);
--- /dev/null
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_H
+#define APUSYS_H
+
+#define MODULE_TAG "[APUSYS]"
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <inttypes.h>
+
+/* TF-A system header */
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+/* Vendor header */
+#include "apusys.h"
+#include "apusys_power.h"
+#include <mtk_mmap_pool.h>
+
+static int apu_poll(uintptr_t reg, uint32_t mask, uint32_t value, uint32_t timeout_us)
+{
+ uint32_t reg_val, count;
+
+ count = timeout_us / APU_POLL_STEP_US;
+ if (count == 0) {
+ count = 1;
+ }
+
+ do {
+ reg_val = mmio_read_32(reg);
+ if ((reg_val & mask) == value) {
+ return 0;
+ }
+
+ udelay(APU_POLL_STEP_US);
+ } while (--count);
+
+ ERROR(MODULE_TAG "Timeout polling APU register %#" PRIxPTR "\n", reg);
+ ERROR(MODULE_TAG "Read value 0x%x, expected 0x%x\n", reg_val,
+ (value == 0U) ? (reg_val & ~mask) : (reg_val | mask));
+
+ return -1;
+}
+
+static void get_pll_pcw(const uint32_t clk_rate, uint32_t *r1, uint32_t *r2)
+{
+ unsigned int fvco = clk_rate;
+ unsigned int pcw_val;
+ unsigned int postdiv_val = 1;
+ unsigned int postdiv_reg = 0;
+
+ while (fvco <= OUT_CLK_FREQ_MIN) {
+ postdiv_val = postdiv_val << 1;
+ postdiv_reg = postdiv_reg + 1;
+ fvco = fvco << 1;
+ }
+
+ pcw_val = (fvco * (1 << DDS_SHIFT)) / BASIC_CLK_FREQ;
+
+ if (postdiv_reg == 0) {
+ pcw_val = pcw_val * 2;
+ postdiv_val = postdiv_val << 1;
+ postdiv_reg = postdiv_reg + 1;
+ }
+
+ *r1 = postdiv_reg;
+ *r2 = pcw_val;
+}
+
+static void apu_pll_init(void)
+{
+ const uint32_t pll_hfctl_cfg[PLL_NUM] = {
+ PLL4HPLL_FHCTL0_CFG,
+ PLL4HPLL_FHCTL1_CFG,
+ PLL4HPLL_FHCTL2_CFG,
+ PLL4HPLL_FHCTL3_CFG
+ };
+ const uint32_t pll_con1[PLL_NUM] = {
+ PLL4H_PLL1_CON1,
+ PLL4H_PLL2_CON1,
+ PLL4H_PLL3_CON1,
+ PLL4H_PLL4_CON1
+ };
+ const uint32_t pll_fhctl_dds[PLL_NUM] = {
+ PLL4HPLL_FHCTL0_DDS,
+ PLL4HPLL_FHCTL1_DDS,
+ PLL4HPLL_FHCTL2_DDS,
+ PLL4HPLL_FHCTL3_DDS
+ };
+ const uint32_t pll_freq_out[PLL_NUM] = {
+ APUPLL0_DEFAULT_FREQ,
+ APUPLL1_DEFAULT_FREQ,
+ APUPLL2_DEFAULT_FREQ,
+ APUPLL3_DEFAULT_FREQ
+ };
+ uint32_t pcw_val, posdiv_val;
+ int pll_idx;
+
+ mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_RST_CON, PLL4H_PLL_HP_SWRSTB);
+ mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_HP_EN, PLL4H_PLL_HP_EN);
+ mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_CLK_CON, PLL4H_PLL_HP_CLKEN);
+
+ for (pll_idx = 0; pll_idx < PLL_NUM; pll_idx++) {
+ mmio_setbits_32(APU_PLL_BASE + pll_hfctl_cfg[pll_idx], (FHCTL0_EN | SFSTR0_EN));
+
+ posdiv_val = 0;
+ pcw_val = 0;
+ get_pll_pcw(pll_freq_out[pll_idx], &posdiv_val, &pcw_val);
+
+ mmio_clrsetbits_32(APU_PLL_BASE + pll_con1[pll_idx],
+ (RG_PLL_POSDIV_MASK << RG_PLL_POSDIV_SFT),
+ (posdiv_val << RG_PLL_POSDIV_SFT));
+ mmio_write_32(APU_PLL_BASE + pll_fhctl_dds[pll_idx],
+ (FHCTL_PLL_TGL_ORG | pcw_val));
+ }
+}
+
+static void apu_acc_init(void)
+{
+ mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR0, CGEN_SOC);
+ mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET0, HW_CTRL_EN);
+
+ mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR1, CGEN_SOC);
+ mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET1, HW_CTRL_EN);
+
+ mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR2, CGEN_SOC);
+ mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET2, HW_CTRL_EN);
+ mmio_write_32(APU_ACC_BASE + APU_ACC_AUTO_CTRL_SET2, CLK_REQ_SW_EN);
+
+ mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR3, CGEN_SOC);
+ mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET3, HW_CTRL_EN);
+ mmio_write_32(APU_ACC_BASE + APU_ACC_AUTO_CTRL_SET3, CLK_REQ_SW_EN);
+
+ mmio_write_32(APU_ACC_BASE + APU_ACC_CLK_INV_EN_SET, CLK_INV_EN);
+}
+
+static void apu_buck_off_cfg(void)
+{
+ mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_PROT_REQ_SET);
+ udelay(10);
+
+ mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_ELS_EN_SET);
+ udelay(10);
+
+ mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_AO_RST_B_CLR);
+ udelay(10);
+}
+
+static void apu_pcu_init(void)
+{
+ uint32_t vapu_en_offset = BUCK_VAPU_PMIC_REG_EN_ADDR;
+ uint32_t vapu_sram_en_offset = BUCK_VAPU_SRAM_PMIC_REG_EN_ADDR;
+
+ mmio_write_32(APU_PCU_BASE + APU_PCU_CTRL_SET, AUTO_BUCK_EN);
+
+ mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_STEP_SEL, BUCK_ON_OFF_CMD_EN);
+
+ mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_DAT0_L,
+ ((vapu_sram_en_offset << BUCK_OFFSET_SFT) + BUCK_ON_CMD));
+ mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_DAT0_H, CMD_OP);
+
+ mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_DAT1_L,
+ ((vapu_en_offset << BUCK_OFFSET_SFT) + BUCK_ON_CMD));
+ mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_DAT1_H, CMD_OP);
+
+ mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_OFF_DAT0_L,
+ ((vapu_en_offset << BUCK_OFFSET_SFT) + BUCK_OFF_CMD));
+ mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_OFF_DAT0_H, CMD_OP);
+
+ mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_OFF_DAT1_L,
+ ((vapu_sram_en_offset << BUCK_OFFSET_SFT) + BUCK_OFF_CMD));
+ mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_OFF_DAT1_H, CMD_OP);
+
+ mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_SLE0, APU_PCU_BUCK_ON_SETTLE_TIME);
+ mmio_write_32(APU_PCU_BASE + APU_PCU_BUCK_ON_SLE1, APU_PCU_BUCK_ON_SETTLE_TIME);
+}
+
+static void apu_rpclite_init(void)
+{
+ const uint32_t sleep_type_offset[] = {
+ APU_RPC_SW_TYPE2,
+ APU_RPC_SW_TYPE3,
+ APU_RPC_SW_TYPE4,
+ APU_RPC_SW_TYPE5,
+ APU_RPC_SW_TYPE6,
+ APU_RPC_SW_TYPE7,
+ APU_RPC_SW_TYPE8,
+ APU_RPC_SW_TYPE9
+ };
+ int ofs_arr_size = ARRAY_SIZE(sleep_type_offset);
+ int ofs_idx;
+
+ for (ofs_idx = 0 ; ofs_idx < ofs_arr_size ; ofs_idx++) {
+ mmio_clrbits_32(APU_ACX0_RPC_LITE_BASE + sleep_type_offset[ofs_idx],
+ SW_TYPE);
+ }
+
+ mmio_setbits_32(APU_ACX0_RPC_LITE_BASE + APU_RPC_TOP_SEL, RPC_CTRL);
+}
+
+static void apu_rpc_init(void)
+{
+ mmio_clrbits_32(APU_RPC_BASE + APU_RPC_SW_TYPE0, SW_TYPE);
+ mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL, RPC_TOP_CTRL);
+ mmio_setbits_32(APU_RPC_BASE + APU_RPC_TOP_SEL_1, RPC_TOP_CTRL1);
+}
+
+static int apu_are_init(void)
+{
+ int ret;
+ int are_id = 0;
+ const uint32_t are_base[APU_ARE_NUM] = { APU_ARE0_BASE, APU_ARE1_BASE, APU_ARE2_BASE };
+ const uint32_t are_entry2_cfg_l[APU_ARE_NUM] = {
+ ARE0_ENTRY2_CFG_L,
+ ARE1_ENTRY2_CFG_L,
+ ARE2_ENTRY2_CFG_L
+ };
+
+ mmio_setbits_32(APU_AO_CTL_BASE + CSR_DUMMY_0_ADDR, VCORE_ARE_REQ);
+
+ ret = apu_poll(APU_ARE2_BASE + APU_ARE_GLO_FSM, ARE_GLO_FSM_IDLE, ARE_GLO_FSM_IDLE,
+ APU_ARE_POLLING_TIMEOUT_US);
+ if (ret != 0) {
+ ERROR(MODULE_TAG "[%s][%d] ARE init timeout\n",
+ __func__, __LINE__);
+ return ret;
+ }
+
+ for (are_id = APU_ARE0; are_id < APU_ARE_NUM; are_id++) {
+ mmio_write_32(are_base[are_id] + APU_ARE_ENTRY0_SRAM_H, ARE_ENTRY0_SRAM_H_INIT);
+ mmio_write_32(are_base[are_id] + APU_ARE_ENTRY0_SRAM_L, ARE_ENTRY0_SRAM_L_INIT);
+
+ mmio_write_32(are_base[are_id] + APU_ARE_ENTRY1_SRAM_H, ARE_ENTRY1_SRAM_H_INIT);
+ mmio_write_32(are_base[are_id] + APU_ARE_ENTRY1_SRAM_L, ARE_ENTRY1_SRAM_L_INIT);
+
+ mmio_write_32(are_base[are_id] + APU_ARE_ENTRY2_SRAM_H, ARE_ENTRY_CFG_H);
+ mmio_write_32(are_base[are_id] + APU_ARE_ENTRY2_SRAM_L, are_entry2_cfg_l[are_id]);
+
+ mmio_read_32(are_base[are_id] + APU_ARE_ENTRY2_SRAM_H);
+ mmio_read_32(are_base[are_id] + APU_ARE_ENTRY2_SRAM_L);
+
+ mmio_write_32(are_base[are_id] + APU_ARE_INI_CTRL, ARE_CONFG_INI);
+ }
+
+ return ret;
+}
+
+static void apu_aoc_init(void)
+{
+ mmio_clrbits_32(SPM_BASE + APUSYS_BUCK_ISOLATION, IPU_EXT_BUCK_ISO);
+ mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_ELS_EN_CLR);
+ udelay(10);
+
+ mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_AO_RST_B_SET);
+ udelay(10);
+
+ mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, BUCK_PROT_REQ_CLR);
+ udelay(10);
+
+ mmio_write_32(APU_RPC_BASE + APU_RPC_HW_CON, SRAM_AOC_ISO_CLR);
+ udelay(10);
+}
+
+static int init_hw_setting(void)
+{
+ int ret;
+
+ apu_aoc_init();
+ apu_pcu_init();
+ apu_rpc_init();
+ apu_rpclite_init();
+
+ ret = apu_are_init();
+ if (ret != 0) {
+ return ret;
+ }
+
+ apu_pll_init();
+ apu_acc_init();
+ apu_buck_off_cfg();
+
+ return ret;
+}
+
+int apusys_power_init(void)
+{
+ int ret;
+
+ ret = init_hw_setting();
+ if (ret != 0) {
+ ERROR(MODULE_TAG "%s initial fail\n", __func__);
+ } else {
+ INFO(MODULE_TAG "%s initial done\n", __func__);
+ }
+
+ return ret;
+}
--- /dev/null
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_POWER_H
+#define APUSYS_POWER_H
+
+#include <platform_def.h>
+
+enum APU_CLKSRC_ID {
+ PLL_CONN = 0, /* MNOC */
+ PLL_UP,
+ PLL_VPU,
+ PLL_DLA,
+ PLL_NUM,
+};
+
+enum APU_ARE_ID {
+ APU_ARE0 = 0,
+ APU_ARE1,
+ APU_ARE2,
+ APU_ARE_NUM,
+};
+
+#define APU_POLL_STEP_US (5)
+
+#define OUT_CLK_FREQ_MIN (1500)
+#define BASIC_CLK_FREQ (26)
+#define DDS_SHIFT (14)
+
+#define APUPLL0_DEFAULT_FREQ (900)
+#define APUPLL1_DEFAULT_FREQ (832)
+#define APUPLL2_DEFAULT_FREQ (700)
+#define APUPLL3_DEFAULT_FREQ (700)
+
+#define APU_TOP_ON_POLLING_TIMEOUT_US (10000)
+#define APU_TOP_OFF_POLLING_TIMEOUT_US (5 * APU_TOP_ON_POLLING_TIMEOUT_US)
+#define APU_ARE_POLLING_TIMEOUT_US (10000)
+
+/* APU related reg */
+#define APU_RPC_BASE (APU_RPCTOP)
+#define APU_PCU_BASE (APU_PCUTOP)
+#define APU_ARE0_BASE (APU_ARETOP_ARE0)
+#define APU_ARE1_BASE (APU_ARETOP_ARE1)
+#define APU_ARE2_BASE (APU_ARETOP_ARE2)
+#define APU_AO_CTL_BASE (APU_AO_CTRL)
+#define APU_PLL_BASE (APU_PLL)
+#define APU_ACC_BASE (APU_ACC)
+#define APU_ACX0_RPC_LITE_BASE (APU_ACX0_RPC_LITE)
+
+/* RPC offset define */
+#define APU_RPC_TOP_SEL (0x0004)
+#define APU_RPC_TOP_SEL_1 (0x0018)
+#define APU_RPC_HW_CON (0x001c)
+#define APU_RPC_SW_TYPE0 (0x0200)
+
+/* RPC control */
+#define SRAM_AOC_ISO_CLR BIT(7)
+#define BUCK_ELS_EN_SET BIT(10)
+#define BUCK_ELS_EN_CLR BIT(11)
+#define BUCK_AO_RST_B_SET BIT(12)
+#define BUCK_AO_RST_B_CLR BIT(13)
+#define BUCK_PROT_REQ_SET BIT(14)
+#define BUCK_PROT_REQ_CLR BIT(15)
+#define SW_TYPE BIT(1)
+#define RPC_CTRL (0x0000009e)
+#define RPC_TOP_CTRL (0x0800501e)
+#define RPC_TOP_CTRL1 BIT(20)
+
+/* PLL offset define */
+#define PLL4H_PLL1_CON1 (0x000c)
+#define PLL4H_PLL2_CON1 (0x001c)
+#define PLL4H_PLL3_CON1 (0x002c)
+#define PLL4H_PLL4_CON1 (0x003c)
+#define PLL4HPLL_FHCTL_HP_EN (0x0e00)
+#define PLL4HPLL_FHCTL_CLK_CON (0x0e08)
+#define PLL4HPLL_FHCTL_RST_CON (0x0e0c)
+#define PLL4HPLL_FHCTL0_CFG (0x0e3c)
+#define PLL4HPLL_FHCTL0_DDS (0x0e44)
+#define PLL4HPLL_FHCTL1_CFG (0x0e50)
+#define PLL4HPLL_FHCTL1_DDS (0x0e58)
+#define PLL4HPLL_FHCTL2_CFG (0x0e64)
+#define PLL4HPLL_FHCTL2_DDS (0x0e6c)
+#define PLL4HPLL_FHCTL3_CFG (0x0e78)
+#define PLL4HPLL_FHCTL3_DDS (0x0e80)
+
+/* PLL control */
+#define PLL4H_PLL_HP_EN (0xf)
+#define PLL4H_PLL_HP_CLKEN (0xf)
+#define PLL4H_PLL_HP_SWRSTB (0xf)
+#define FHCTL0_EN BIT(0)
+#define SFSTR0_EN BIT(2)
+#define RG_PLL_POSDIV_MASK (0x7)
+#define RG_PLL_POSDIV_SFT (24)
+#define FHCTL_PLL_TGL_ORG BIT(31)
+
+/* ACC offset define */
+#define APU_ACC_CONFG_SET0 (0x0000)
+#define APU_ACC_CONFG_SET1 (0x0004)
+#define APU_ACC_CONFG_SET2 (0x0008)
+#define APU_ACC_CONFG_SET3 (0x000c)
+#define APU_ACC_CONFG_CLR0 (0x0040)
+#define APU_ACC_CONFG_CLR1 (0x0044)
+#define APU_ACC_CONFG_CLR2 (0x0048)
+#define APU_ACC_CONFG_CLR3 (0x004c)
+#define APU_ACC_CLK_INV_EN_SET (0x00e8)
+#define APU_ACC_AUTO_CTRL_SET2 (0x0128)
+#define APU_ACC_AUTO_CTRL_SET3 (0x012c)
+
+/* ACC control */
+#define CGEN_SOC BIT(2)
+#define HW_CTRL_EN BIT(15)
+#define CLK_REQ_SW_EN BIT(8)
+#define CLK_INV_EN (0xaaa8)
+
+/* ARE offset define */
+#define APU_ARE_INI_CTRL (0x0000)
+#define APU_ARE_GLO_FSM (0x0048)
+#define APU_ARE_ENTRY0_SRAM_H (0x0c00)
+#define APU_ARE_ENTRY0_SRAM_L (0x0800)
+#define APU_ARE_ENTRY1_SRAM_H (0x0c04)
+#define APU_ARE_ENTRY1_SRAM_L (0x0804)
+#define APU_ARE_ENTRY2_SRAM_H (0x0c08)
+#define APU_ARE_ENTRY2_SRAM_L (0x0808)
+
+/* ARE control */
+#define ARE_ENTRY_CFG_H (0x00140000)
+#define ARE0_ENTRY2_CFG_L (0x004e0804)
+#define ARE1_ENTRY2_CFG_L (0x004e0806)
+#define ARE2_ENTRY2_CFG_L (0x004e0807)
+#define ARE_GLO_FSM_IDLE BIT(0)
+#define ARE_ENTRY0_SRAM_H_INIT (0x12345678)
+#define ARE_ENTRY0_SRAM_L_INIT (0x89abcdef)
+#define ARE_ENTRY1_SRAM_H_INIT (0xfedcba98)
+#define ARE_ENTRY1_SRAM_L_INIT (0x76543210)
+#define ARE_CONFG_INI BIT(2)
+
+/* SPM offset define */
+#define APUSYS_BUCK_ISOLATION (0x03ec)
+
+/* SPM control*/
+#define IPU_EXT_BUCK_ISO (0x21)
+
+/* apu_rcx_ao_ctrl */
+#define CSR_DUMMY_0_ADDR (0x0024)
+
+/* apu_rcx_ao_ctrl control */
+#define VCORE_ARE_REQ BIT(2)
+
+/* PCU offset define */
+#define APU_PCU_CTRL_SET (0x0000)
+#define APU_PCU_BUCK_STEP_SEL (0x0030)
+#define APU_PCU_BUCK_ON_DAT0_L (0x0080)
+#define APU_PCU_BUCK_ON_DAT0_H (0x0084)
+#define APU_PCU_BUCK_ON_DAT1_L (0x0088)
+#define APU_PCU_BUCK_ON_DAT1_H (0x008c)
+#define APU_PCU_BUCK_OFF_DAT0_L (0x00a0)
+#define APU_PCU_BUCK_OFF_DAT0_H (0x00a4)
+#define APU_PCU_BUCK_OFF_DAT1_L (0x00a8)
+#define APU_PCU_BUCK_OFF_DAT1_H (0x00ac)
+#define APU_PCU_BUCK_ON_SLE0 (0x00c0)
+#define APU_PCU_BUCK_ON_SLE1 (0x00c4)
+#define APU_PCU_BUCK_ON_SETTLE_TIME (0x012c)
+
+/* PCU initial data */
+#define MT6359P_RG_BUCK_VMODEM_EN_ADDR (0x1688)
+#define MT6359P_RG_LDO_VSRAM_MD_EN_ADDR (0x1f2e)
+#define BUCK_VAPU_PMIC_REG_EN_ADDR MT6359P_RG_BUCK_VMODEM_EN_ADDR
+#define BUCK_VAPU_SRAM_PMIC_REG_EN_ADDR MT6359P_RG_LDO_VSRAM_MD_EN_ADDR
+
+/* PCU control */
+#define AUTO_BUCK_EN BIT(16)
+#define BUCK_ON_OFF_CMD_EN (0x33)
+#define BUCK_OFFSET_SFT (16)
+#define BUCK_ON_CMD (0x1)
+#define BUCK_OFF_CMD (0x0)
+#define CMD_OP (0x4)
+
+/* RPC lite offset define */
+#define APU_RPC_SW_TYPE2 (0x0208)
+#define APU_RPC_SW_TYPE3 (0x020c)
+#define APU_RPC_SW_TYPE4 (0x0210)
+#define APU_RPC_SW_TYPE5 (0x0214)
+#define APU_RPC_SW_TYPE6 (0x0218)
+#define APU_RPC_SW_TYPE7 (0x021c)
+#define APU_RPC_SW_TYPE8 (0x0220)
+#define APU_RPC_SW_TYPE9 (0x0224)
+
+int apusys_power_init(void);
+
+#endif /* APUSYS_POWER_H */
--- /dev/null
+#
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := apusys_${MTK_SOC}
+
+LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_power.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
--- /dev/null
+#
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := apusys
+
+LOCAL_SRCS-y:= ${LOCAL_DIR}/apusys.c
+
+PLAT_INCLUDES += -I${LOCAL_DIR} -I${LOCAL_DIR}/${MTK_SOC}
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
+
+SUB_RULES-y := ${LOCAL_DIR}/${MTK_SOC}
+
+$(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES-y)))
#define TOPCKGEN_BASE (IO_PHYS)
+/*******************************************************************************
+ * APUSYS related constants
+ ******************************************************************************/
+#define BCRM_FMEM_PDN_BASE (IO_PHYS + 0x00276000)
+#define APU_RPCTOP (IO_PHYS + 0x090f0000)
+#define APU_PCUTOP (IO_PHYS + 0x090f1000)
+#define APU_AO_CTRL (IO_PHYS + 0x090f2000)
+#define APU_PLL (IO_PHYS + 0x090f3000)
+#define APU_ACC (IO_PHYS + 0x090f4000)
+#define APU_ARETOP_ARE0 (IO_PHYS + 0x090f6000)
+#define APU_ARETOP_ARE1 (IO_PHYS + 0x090f7000)
+#define APU_ARETOP_ARE2 (IO_PHYS + 0x090f8000)
+#define APU_ACX0_RPC_LITE (IO_PHYS + 0x09140000)
+#define BCRM_FMEM_PDN_SIZE (0x1000)
+
/*******************************************************************************
* AUDIO related constants
******************************************************************************/
MODULES-y += $(MTK_PLAT)/lib/mtk_init
MODULES-y += $(MTK_PLAT)/lib/pm
MODULES-y += $(MTK_PLAT)/lib/system_reset
+MODULES-y += $(MTK_PLAT)/drivers/apusys
MODULES-y += $(MTK_PLAT)/drivers/audio
MODULES-y += $(MTK_PLAT)/drivers/cirq
MODULES-y += $(MTK_PLAT)/drivers/cpu_pm
projects / arm-tf.git / commitdiff