drm/i915: Add the missing adls vswing tables

adls is supposed to use special buf trans tables. Add what's
missing.

v2: Drop the RBR/HBR table since it's the same as for tgl

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210608073603.2408-18-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index a456823df102dd68e07a514bc27496e8bdf40220..63b1ae830d9a0f66a67c2cf9c5f92dcf3759e797 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1000,6 +1000,63 @@ static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_h
        .num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr2_hbr3),
 };
 
+static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
+                                                       /* NT mV Trans mV db    */
+       { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
+       { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },     /* 350   500      3.1   */
+       { .cnl = { 0xC, 0x63, 0x30, 0x00, 0x0F } },     /* 350   700      6.0   */
+       { .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },     /* 350   900      8.2   */
+       { .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },     /* 500   500      0.0   */
+       { .cnl = { 0xC, 0x63, 0x37, 0x00, 0x08 } },     /* 500   700      2.9   */
+       { .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } },     /* 500   900      5.1   */
+       { .cnl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } },     /* 650   700      0.6   */
+       { .cnl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } },     /* 600   900      3.5   */
+       { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 900   900      0.0   */
+};
+
+static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
+       .entries = _adls_combo_phy_ddi_translations_dp_hbr2_hbr3,
+       .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_dp_hbr2_hbr3),
+};
+
+static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr2[] = {
+                                                       /* NT mV Trans mV db    */
+       { .cnl = { 0x9, 0x70, 0x3C, 0x00, 0x03 } },     /* 200   200      0.0   */
+       { .cnl = { 0x9, 0x6D, 0x3A, 0x00, 0x05 } },     /* 200   250      1.9   */
+       { .cnl = { 0x9, 0x7F, 0x36, 0x00, 0x09 } },     /* 200   300      3.5   */
+       { .cnl = { 0x4, 0x59, 0x32, 0x00, 0x0D } },     /* 200   350      4.9   */
+       { .cnl = { 0x2, 0x77, 0x3A, 0x00, 0x05 } },     /* 250   250      0.0   */
+       { .cnl = { 0x2, 0x7F, 0x38, 0x00, 0x07 } },     /* 250   300      1.6   */
+       { .cnl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } },     /* 250   350      2.9   */
+       { .cnl = { 0x4, 0x5E, 0x3D, 0x00, 0x04 } },     /* 300   300      0.0   */
+       { .cnl = { 0x4, 0x65, 0x38, 0x00, 0x07 } },     /* 300   350      1.3   */
+       { .cnl = { 0x4, 0x6F, 0x3A, 0x00, 0x05 } },     /* 350   350      0.0   */
+};
+
+static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr2 = {
+       .entries = _adls_combo_phy_ddi_translations_edp_hbr2,
+       .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr2),
+};
+
+static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr3[] = {
+                                                       /* NT mV Trans mV db    */
+       { .cnl = { 0xA, 0x5E, 0x34, 0x00, 0x0B } },     /* 350   350      0.0   */
+       { .cnl = { 0xA, 0x69, 0x32, 0x00, 0x0D } },     /* 350   500      3.1   */
+       { .cnl = { 0xC, 0x74, 0x31, 0x00, 0x0E } },     /* 350   700      6.0   */
+       { .cnl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } },     /* 350   900      8.2   */
+       { .cnl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } },     /* 500   500      0.0   */
+       { .cnl = { 0xC, 0x7F, 0x34, 0x00, 0x0B } },     /* 500   700      2.9   */
+       { .cnl = { 0x6, 0x7F, 0x33, 0x00, 0x0C } },     /* 500   900      5.1   */
+       { .cnl = { 0xC, 0x7F, 0x3F, 0x00, 0x00 } },     /* 650   700      0.6   */
+       { .cnl = { 0x6, 0x7F, 0x3C, 0x00, 0x03 } },     /* 600   900      3.5   */
+       { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 900   900      0.0   */
+};
+
+static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr3 = {
+       .entries = _adls_combo_phy_ddi_translations_edp_hbr3,
+       .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr3),
+};
+
 static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_ddi_translations_dp_hbr[] = {
                                        /* VS   pre-emp Non-trans mV    Pre-emph dB */
        { .dkl = { 0x7, 0x0, 0x01 } },  /* 0    0       400mV           0 dB */
@@ -1562,6 +1619,48 @@ rkl_get_combo_buf_trans(struct intel_encoder *encoder,
                return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
+static const struct intel_ddi_buf_trans *
+adls_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+                           const struct intel_crtc_state *crtc_state,
+                           int *n_entries)
+{
+       if (crtc_state->port_clock > 270000)
+               return intel_get_buf_trans(&adls_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries);
+       else
+               return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, n_entries);
+}
+
+static const struct intel_ddi_buf_trans *
+adls_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+                            const struct intel_crtc_state *crtc_state,
+                            int *n_entries)
+{
+       struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+       struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+       if (crtc_state->port_clock > 540000)
+               return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr3, n_entries);
+       else if (i915->vbt.edp.hobl && !intel_dp->hobl_failed)
+               return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, n_entries);
+       else if (i915->vbt.edp.low_vswing)
+               return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr2, n_entries);
+       else
+               return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
+}
+
+static const struct intel_ddi_buf_trans *
+adls_get_combo_buf_trans(struct intel_encoder *encoder,
+                        const struct intel_crtc_state *crtc_state,
+                        int *n_entries)
+{
+       if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+               return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries);
+       else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+               return adls_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
+       else
+               return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
+}
+
 static const struct intel_ddi_buf_trans *
 tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
                         const struct intel_crtc_state *crtc_state,
@@ -1642,6 +1741,8 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
                        encoder->get_buf_trans = tgl_get_combo_buf_trans;
                else
                        encoder->get_buf_trans = adlp_get_dkl_buf_trans;
+       } else if (IS_ALDERLAKE_S(i915)) {
+               encoder->get_buf_trans = adls_get_combo_buf_trans;
        } else if (IS_ROCKETLAKE(i915)) {
                encoder->get_buf_trans = rkl_get_combo_buf_trans;
        } else if (IS_DG1(i915)) {