struct dma_fence_cb cb;
};
+/**
+ * amdgpu_vm_level_shift - return the addr shift for each level
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Returns the number of bits the pfn needs to be right shifted for a level.
+ */
+static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
+ unsigned level)
+{
+ if (level != adev->vm_manager.num_level)
+ return 9 * (adev->vm_manager.num_level - level - 1) +
+ adev->vm_manager.block_size;
+ else
+ /* For the page tables on the leaves */
+ return 0;
+}
+
/**
* amdgpu_vm_num_entries - return the number of entries in a PD/PT
*
uint64_t saddr, uint64_t eaddr,
unsigned level)
{
- unsigned shift = (adev->vm_manager.num_level - level) *
- adev->vm_manager.block_size;
+ unsigned shift = amdgpu_vm_level_shift(adev, level);
unsigned pt_idx, from, to;
int r;
u64 flags;
struct amdgpu_vm_pt **entry,
struct amdgpu_vm_pt **parent)
{
- unsigned idx, level = p->adev->vm_manager.num_level;
+ unsigned level = 0;
*parent = NULL;
*entry = &p->vm->root;
while ((*entry)->entries) {
- idx = addr >> (p->adev->vm_manager.block_size * level--);
+ unsigned idx = addr >> amdgpu_vm_level_shift(p->adev, level++);
+
idx %= amdgpu_bo_size((*entry)->base.bo) / 8;
*parent = *entry;
*entry = &(*entry)->entries[idx];
}
- if (level)
+ if (level != p->adev->vm_manager.num_level)
*entry = NULL;
}