#define DTS_DR_OFFSET 0x1C
#define DTS_SR_OFFSET 0x20
#define DTS_ITENR_OFFSET 0x24
-#define DTS_CIFR_OFFSET 0x28
+#define DTS_ICIFR_OFFSET 0x28
/* DTS_CFGR1 register mask definitions */
#define HSREF_CLK_DIV_MASK GENMASK(30, 24)
value = readl_relaxed(sensor->base + DTS_SR_OFFSET);
if ((value & LOW_THRESHOLD) == LOW_THRESHOLD)
- writel_relaxed(LOW_THRESHOLD, sensor->base + DTS_CIFR_OFFSET);
+ writel_relaxed(LOW_THRESHOLD, sensor->base + DTS_ICIFR_OFFSET);
if ((value & HIGH_THRESHOLD) == HIGH_THRESHOLD)
- writel_relaxed(HIGH_THRESHOLD, sensor->base + DTS_CIFR_OFFSET);
+ writel_relaxed(HIGH_THRESHOLD, sensor->base + DTS_ICIFR_OFFSET);
thermal_zone_device_update(sensor->th_dev, THERMAL_EVENT_UNSPECIFIED);
*/
/* Make sure LOW_THRESHOLD IT is clear before enabling */
- writel_relaxed(LOW_THRESHOLD, sensor->base + DTS_CIFR_OFFSET);
+ writel_relaxed(LOW_THRESHOLD, sensor->base + DTS_ICIFR_OFFSET);
/* Enable IT generation for low threshold */
value = readl_relaxed(sensor->base + DTS_ITENR_OFFSET);
/* Enable the low temperature threshold if needed */
if (sensor->low_temp_enabled) {
/* Make sure HIGH_THRESHOLD IT is clear before enabling */
- writel_relaxed(HIGH_THRESHOLD, sensor->base + DTS_CIFR_OFFSET);
+ writel_relaxed(HIGH_THRESHOLD, sensor->base + DTS_ICIFR_OFFSET);
/* Enable IT generation for high threshold */
value |= HIGH_THRESHOLD;