gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler

Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins).
The hwirq base for each sgpio bank should be multiples of 64 rather than
multiples of 32.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 3d6ef37a7702a6ae775c1fb863e5882062dec372..b3a9b8488f11de696f0e00e42d7620c09b343c13 100644 (file)
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
                reg = ioread32(bank_reg(data, bank, reg_irq_status));
 
                for_each_set_bit(p, &reg, 32)
-                       generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2);
+                       generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
        }
 
        chained_irq_exit(ic, desc);