drm/i915/xehpsdv: Define MOCS table for XeHP SDV

Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a
dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to
memory for L3 destined transaction" and L3_LKP to "enable Lookup for
uncacheable accesses".

Bspec: 45101
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210904003544.2422282-2-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index f47521b8e941bad2184f3d7c3c54eab2e3a33c34..8c3fbf4f323b9c79f330e7470bd93d86a180a61b 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -42,6 +42,8 @@ struct drm_i915_mocs_table {
 #define L3_ESC(value)          ((value) << 0)
 #define L3_SCC(value)          ((value) << 1)
 #define _L3_CACHEABILITY(value)        ((value) << 4)
+#define L3_GLBGO(value)                ((value) << 6)
+#define L3_LKUP(value)         ((value) << 7)
 
 /* Helper defines */
 #define GEN9_NUM_MOCS_ENTRIES  64  /* 63-64 are reserved, but configured. */
@@ -343,6 +345,31 @@ static const struct drm_i915_mocs_entry gen12_mocs_table[] = {
                   L3_3_WB),
 };
 
+static const struct drm_i915_mocs_entry xehpsdv_mocs_table[] = {
+       /* wa_1608975824 */
+       MOCS_ENTRY(0, 0, L3_3_WB | L3_LKUP(1)),
+
+       /* UC - Coherent; GO:L3 */
+       MOCS_ENTRY(1, 0, L3_1_UC | L3_LKUP(1)),
+       /* UC - Coherent; GO:Memory */
+       MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
+       /* UC - Non-Coherent; GO:Memory */
+       MOCS_ENTRY(3, 0, L3_1_UC | L3_GLBGO(1)),
+       /* UC - Non-Coherent; GO:L3 */
+       MOCS_ENTRY(4, 0, L3_1_UC),
+
+       /* WB */
+       MOCS_ENTRY(5, 0, L3_3_WB | L3_LKUP(1)),
+
+       /* HW Reserved - SW program but never use. */
+       MOCS_ENTRY(48, 0, L3_3_WB | L3_LKUP(1)),
+       MOCS_ENTRY(49, 0, L3_1_UC | L3_LKUP(1)),
+       MOCS_ENTRY(60, 0, L3_1_UC),
+       MOCS_ENTRY(61, 0, L3_1_UC),
+       MOCS_ENTRY(62, 0, L3_1_UC),
+       MOCS_ENTRY(63, 0, L3_1_UC),
+};
+
 enum {
        HAS_GLOBAL_MOCS = BIT(0),
        HAS_ENGINE_MOCS = BIT(1),
@@ -372,7 +399,13 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
        memset(table, 0, sizeof(struct drm_i915_mocs_table));
 
        table->unused_entries_index = I915_MOCS_PTE;
-       if (IS_DG1(i915)) {
+       if (IS_XEHPSDV(i915)) {
+               table->size = ARRAY_SIZE(xehpsdv_mocs_table);
+               table->table = xehpsdv_mocs_table;
+               table->uc_index = 2;
+               table->n_entries = GEN9_NUM_MOCS_ENTRIES;
+               table->unused_entries_index = 5;
+       } else if (IS_DG1(i915)) {
                table->size = ARRAY_SIZE(dg1_mocs_table);
                table->table = dg1_mocs_table;
                table->uc_index = 1;