Merge tag 'trbe-cortex-a510-errata' of gitolite.kernel.org:pub/scm/linux/kernel/git...

coresight: trbe: Workaround Cortex-A510 erratas

This pull request is providing arm64 definitions to support
TRBE Cortex-A510 erratas.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
* tag 'trbe-cortex-a510-errata' of gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux:
  arm64: errata: Add detection for TRBE trace data corruption
  arm64: errata: Add detection for TRBE invalid prohibited states
  arm64: errata: Add detection for TRBE ignored system register writes
  arm64: Add Cortex-A510 CPU part definition

diff --cc Documentation/arm64/silicon-errata.rst
Simple merge

diff --cc arch/arm64/Kconfig
Simple merge

diff --cc arch/arm64/include/asm/cputype.h
index 657eeb06c7847d19a28c48ba4d11ffbac57fb2ea,e8fdc10395b6a6e0cdc74619b0bcc823c553c26a..999b9149f85681e014d7fa6ab539edcfc621cdcb
--- 1/arch/arm64/include/asm/cputype.h
--- 2/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@@ -73,8 -73,8 +73,9 @@@
  #define ARM_CPU_PART_CORTEX_A76               0xD0B
  #define ARM_CPU_PART_NEOVERSE_N1      0xD0C
  #define ARM_CPU_PART_CORTEX_A77               0xD0D
+ #define ARM_CPU_PART_CORTEX_A510      0xD46
  #define ARM_CPU_PART_CORTEX_A710      0xD47
 +#define ARM_CPU_PART_CORTEX_X2                0xD48
  #define ARM_CPU_PART_NEOVERSE_N2      0xD49
  
  #define APM_CPU_PART_POTENZA          0x000
@@@ -116,8 -116,8 +117,9 @@@
  #define MIDR_CORTEX_A76       MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
  #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
  #define MIDR_CORTEX_A77       MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
+ #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
  #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
 +#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
  #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
  #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
  #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

diff --cc arch/arm64/kernel/cpu_errata.c
Simple merge